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Horizontal counter
Posted by
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11 May 2005
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The next stage is the horizontal counter.
The 7 MHz clock signal enters F8 which is a 4-bit binary counter. The clock is divided in half producing the 1H signal which is the low bit of the horizontal counter. Each stage of F8 divides the signal in half again producing 2H, 4H, and 8H. F9 continues the division producing 16H, 32H, 64H and 128H. Finally the clock is divided in half one more time by F6 to produce 256H and an inverted version called /256H. (I use the ‘/’ before a signal name to indicate that it’s an active low signal).
The NAND gate F7 is used to reset the counters when the end of a horizontal line has been reached. The gate is connected to 256H, 128H, 64H, 4H and 2H, so the output of the gate goes low when count 454 is reached (256+128+64+4+2). The output of the NAND gate will get clocked through E7 on the next rising edge of CLK (actually the 455th count), to the HRESET signal. HRESET will reset the horizontal counter back to 0. On the next clock the output of the NAND will be high, which will be clocked through E7 and return HRESET high, thus allowing the counters to start counting again.
The 7 MHz clock signal enters F8 which is a 4-bit binary counter. The clock is divided in half producing the 1H signal which is the low bit of the horizontal counter. Each stage of F8 divides the signal in half again producing 2H, 4H, and 8H. F9 continues the division producing 16H, 32H, 64H and 128H. Finally the clock is divided in half one more time by F6 to produce 256H and an inverted version called /256H. (I use the ‘/’ before a signal name to indicate that it’s an active low signal).
The NAND gate F7 is used to reset the counters when the end of a horizontal line has been reached. The gate is connected to 256H, 128H, 64H, 4H and 2H, so the output of the gate goes low when count 454 is reached (256+128+64+4+2). The output of the NAND gate will get clocked through E7 on the next rising edge of CLK (actually the 455th count), to the HRESET signal. HRESET will reset the horizontal counter back to 0. On the next clock the output of the NAND will be high, which will be clocked through E7 and return HRESET high, thus allowing the counters to start counting again.
One question; why is QA looped back to CLKB?