Allowing eproms in DigDug Carts...

[PacManPlus]

Hi:

 

Is it possible to wire an eprom in a Dig-Dug cart in order to be able to take advantage of the RAM in it?

 

I have some hacks I would like to put in it, if it's possible.

 

I tried to do a search, but there are way too many pages that come up :-/

 

Thanks in advance,

Bob

[Cybergoth]

Hi there!

 

I'll just pretend I didn't see that...

 

Greetings,

Manuel

[PacManPlus]

Why? did I say something wrong?

[djmips]

I think he's just 'kidding' (but actually he's serious) about you messing with the sanctity of original cartridges. There's only 'n' Dig Dug cartridges in the world and if you really hold the original hardware/carts as being sacred then destroying one is somewhat akin to blasphemy.

 

However, there do seem to be a lot of Dig Dug cartridges around, for sale, around my house, around your house, and I for one think that a Dig Dug cart here or there being sacrificed for some new homebrew prototyping is a fine idea.

 

In my investigation of this same topic, I found that the Sara chip was a seperate unit and that it had been sucessfully harvested and used in other peoples homebrew proto or download carts.

 

The only problem is if you wanted to make a run of carts for sale, where would you get the Sara chips then? Well, converting Dig Dug carts etc then becomes a bit more of an ethical issue but I believe that there will be Sara clones or better available in the near to semi-near future. For instance, supercat for one, has a RAM cart design that is promising.

[PacManPlus]

Thanks for the reply

 

I actually looked up the DigDug rarity number before I posted the question (it's a '2') so I didn't think it was that bad.

 

I don't want to make a run of carts, I just want to make one or two test hacks (of Jr. Pac-Man to be exact - I want to play with changing the mazes). I have the CC2 for the test, but I want to solidify them by putting them on cart for myself when I'm done. I like making labels.

 

Thanks again.

[+batari]

Hi:

 

Is it possible to wire an eprom in a Dig-Dug cart in order to be able to take advantage of the RAM in it?

966586[/snapback]

A while back, I sketched out a very simple design that I thought would replicate the SARA chip (the RAM part of it.) However, some convinced me that it definitely wouldn't work because certain instructions (read-modify-write) wouldn't be supported, and maybe some addressing modes and code in RAM wouldn't work either, so I kind of forgot about it.

 

BUT I recently found out that the SARA chip has exactly the same limitations! However, I cannot find the document that described this behavior for the life of me. If I find it, I will post.

 

Also, if I get a chance, maybe I'll make a prototype of my design using some 74xx chips and an RC circuit just to see if I was right that evening when I wrote the design on the back of an envelope.

[supercat]

Also, if I get a chance, maybe I'll make a prototype of my design using some 74xx chips and an RC circuit just to see if I was right that evening when I wrote the design on the back of an envelope.

966868[/snapback]

 

I think I remember the design in question, and the problem wasn't with read/modify/write instructions (I think mine is the only RAM cartridge design anywhere for the 2600 that handles those cleanly) but rather with indexed writes (which I really don't know how SARA handles).

 

Consider the following two instructions:

 STA $1005
 STA $1000,y ; Y==5

In order to support the first instruction, the processor must generate a RAM write between the time data becomes valid and the time of the next address or data change. In other words, the rising edge of /WE or /CE (whichever happens first) must occur between 420ns and 835ns from time the $1005 address appearing on the bus.

 

In order to support the second instruction, the processor must generate a RAM write sometime between the time data becomes valid on the SECOND cycle and the time of the following address or data change. In other words, the rising edge of /WE or /CE must occur between 1.3us and 1.65us from the time the $1005 address appears on the bus.

 

It's possible to construct a circuit which will go active for the proper time in the first cycle, and then go active again for the proper time in the next cycle, but it's pretty tricky.

 

The other alternative would be to require that the only writes allowed are indexed writes. This was actually part of my original plan, but it can be something of a nuisance.

[djmips]

Hi Fred, I'd really like to see your Sara clone!

 

In other news, from a conversation I had with Curt Vendel, he mentioned that he had some ancient CAD files of the original Sara design on tape and that some day, he would like to retrieve the information and perhaps make it available.

 

It would be nice to see those schematics join the TIA and others here on AtariAge.

[+batari]

Also, if I get a chance, maybe I'll make a prototype of my design using some 74xx chips and an RC circuit just to see if I was right that evening when I wrote the design on the back of an envelope.

966868[/snapback]

 

I think I remember the design in question, and the problem wasn't with read/modify/write instructions (I think mine is the only RAM cartridge design anywhere for the 2600 that handles those cleanly) but rather with indexed writes (which I really don't know how SARA handles).

 

966888[/snapback]

I remember seeing mention that only certain addressing modes were supported as well, and there were page boundary issues with indexing. I still can't find the document I remember reading, and google is turning up nothing.

Hi Fred, I'd really like to see your Sara clone!

 

In other news, from a conversation I had with Curt Vendel, he mentioned that he had some ancient CAD files of the original Sara design on tape and that some day, he would like to retrieve the information and perhaps make it available.

 

It would be nice to see those schematics join the TIA and others here on AtariAge.

I would like to see all of the docs on the Sara chip as well. I did post my design (on the pinned Minigame thread) but it isn't complete. It still needs an RC circuit for timing no matter what, and even then it will be limited in what it can do, if it works at all. But that document about the Sara chip's limitations was encouraging, though I really wish I could find it! I'll check my browser cache now... Maybe it's still there.

[+batari]

Found it: http://www.howell1964.freeserve.co.uk/Atar...a/schematic.htm

 

To quote the site:

Sara is a 128 by 128 RAM that is memory-mapped into the VCS cartridge slot (F000 to FFFF). RAM write addresses are F000 to F07F. RAM read addresses are F080 to F0FF. The RAM read add and write addresses over ride the ROM in that address space. Sara RAM cannot be used as program space, i.e. data storage only.

 

Accessing Sara can be done by most instructions with address modes: absolute, absolute indexed by X, absolute indexed by Y, indexed indirect, or indexed indirect by Y. The exceptions are any instruction that required the 6507 to read RAM, modify the data, and write back to the memory. Also in the indexing modes, the addres plus the index cannot cross a page boundary, where the page boundary size is 256 bytes.

When I read this, I thought the issue was the RMW instructions, but yes, with absolute indexed stores, the address is valid on cycle 4 and 5, and the write is done on the second cycle.

 

Two ways to deal with it:

 

1. Ignore it and make sure that stores always wrap a page (i.e. STA $EFFF,X would work just fine, since the address on the fourth cycle is smaller by $100, and the fifth cycle it fixes up the high byte to be within the correct range and it will write correctly.) Then see if the superchip games can be modified to always wrap a page.

 

2. Use 3 carefully designed RC circuits all triggered by the RAM address range (will be weakly pulled high, but gradually pulled low by the RC when the address is active.) One will be fast, one medium and one slow. The three outputs are then connected to a 3-in XOR, which will create a high-low-high-low signal we need. And yeah, timing is going to be tough to get right.

 

If I get around to doing this, I might try option 1 first, as it might be quite possible and easier to just go in and hack all of the superchip games to conform to option 1...

[Shawn]

If I get around to doing this, I might try option 1 first, as it might be quite possible and easier to just go in and hack all of the superchip games to conform to option 1...

 

 

 

That would be awsome, Hello easy burn of Shooting Arcade & Jr. Pacman!!

Edited November 17, 2005 by silver_surfer

[djmips]

If I get around to doing this, I might try option 1 first, as it might be quite possible and easier to just go in and hack all of the superchip games to conform to option 1...

 

I'd hope that you could make a breakthrough on option 2... I've disassembled Defender 2 to look at a superchip game and made some changes and reassembled (and it's quite a pain to make changes to these games.) The work required to match indexing and possible side effects on the flags. Plus, the extra cycles from page wrapping that would occur not only on the RAM locations but in some cases on ROM locations that are being indexed with the same index register.

 

Pardon the lack of cohesive sentences. It's late.

[+batari]

If I get around to doing this, I might try option 1 first, as it might be quite possible and easier to just go in and hack all of the superchip games to conform to option 1...

 

I'd hope that you could make a breakthrough on option 2... I've disassembled Defender 2 to look at a superchip game and made some changes and reassembled (and it's quite a pain to make changes to these games.) The work required to match indexing and possible side effects on the flags. Plus, the extra cycles from page wrapping that would occur not only on the RAM locations but in some cases on ROM locations that are being indexed with the same index register.

 

Pardon the lack of cohesive sentences. It's late.

967880[/snapback]

I will try, probably in a few weeks. From Supercat's statement here:

the rising edge of /WE or /CE (whichever happens first) must occur between 420ns and 835ns from time the $1005 address appearing on the bus.

...

[for the second cycle] the rising edge of /WE or /CE must occur between 1.3us and 1.65us from the time the $1005 address appears on the bus.

There is some flexibility in timing, which is good. It might work.

[Breakpack]

Thanks for the reply

 

I actually looked up the DigDug rarity number before I posted the question (it's a '2') so I didn't think it was that bad.

 

I don't want to make a run of carts, I just want to make one or two test hacks (of Jr. Pac-Man to be exact - I want to play with changing the mazes).  I have the CC2 for the test, but I want to solidify them by putting them on cart for myself when I'm done.  I like making labels.

 

Thanks again.

966695[/snapback]

 

Ahhh,I smell a Pac Hack a mile away!!Let the man have his Dig Dug chips!

[+batari]

Thanks for the reply

 

I actually looked up the DigDug rarity number before I posted the question (it's a '2') so I didn't think it was that bad.

 

I don't want to make a run of carts, I just want to make one or two test hacks (of Jr. Pac-Man to be exact - I want to play with changing the mazes).  I have the CC2 for the test, but I want to solidify them by putting them on cart for myself when I'm done.  I like making labels.

 

Thanks again.

966695[/snapback]

 

Ahhh,I smell a Pac Hack a mile away!!Let the man have his Dig Dug chips!

968357[/snapback]

I just wrote up a design for F6 plus Superchip in VHDL. It all fits on a 22v10 PLD chip. Also, I found that Digikey has 128 byte SRAM chips for $6 a tube (I think it's per tube? Because $6 each would be a rip off.) Aside from the two chips, you'd just need a few resistors and caps and that's it. Oh, and the EPROM. If this all works, there'd be no need to steal all of those SARA chips

 

If anyone knows VHDL, let me know if this code is screwed. It's a little painful to read since I'm mostly using dataflow and structural VHDL. The only behavioral VHDL is the D_latch (level-triggered ... should I be using something edge-triggered instead?)

sara.vhd.txt

[Cybergoth]

Hi there!

 

I just wrote up a design for F6 plus Superchip in VHDL.  It all fits on a 22v10 PLD chip.  Also, I found that Digikey has 128 byte SRAM chips for $6 a tube (I think it's per tube?  Because $6 each would be a rip off.)  Aside from the two chips, you'd just need a few resistors and caps and that's it.  Oh, and the EPROM.  If this all works, there'd be no need to steal all of those SARA chips

 

This sounds like brilliant news! Please keep us updated!

 

Greetings,

Manuel

[+batari]

I found that Digikey has 128 byte SRAM chips for $6 a tube

968780[/snapback]

Just got my Digikey order in. The SRAM has a multiplexed data/address bus, so it totally unsuitable. I should have checked the datasheet first. I have some spare SRAM chips from old motherboards that I will use for prototyping, but I will need to secure a better source if I am going to lay this out on a board.

 

Does anyone know a good, cheap SRAM chip? It doesn't matter how big the SRAM chips are, only that they must be DIP or PLCC. I can't work with surface mount stuff.

[CPUWIZ]

Does anyone know a good, cheap SRAM chip?  It doesn't matter how big the SRAM chips are, only that they must be DIP or PLCC.  I can't work with surface mount stuff.

973313[/snapback]

 

Not sure what you consider cheap.

 

http://www.jdr.com/interact/item.asp?itemno=gr-staticram

[sku_u]

Hi:

 

Is it possible to wire an eprom in a Dig-Dug cart in order to be able to take advantage of the RAM in it?

 

I have some hacks I would like to put in it, if it's possible.

 

I tried to do a search, but there are way too many pages that come up :-/

 

Thanks in advance,

Bob

966586[/snapback]

 

Not sure, but I'd love to see your creative talents channeled into creating a homebrew and I know I'm not the only one who'd like to see this.

[+batari]

Does anyone know a good, cheap SRAM chip?  It doesn't matter how big the SRAM chips are, only that they must be DIP or PLCC.  I can't work with surface mount stuff.

973313[/snapback]

 

Not sure what you consider cheap.

 

http://www.jdr.com/interact/item.asp?itemno=gr-staticram

973317[/snapback]

Hmm. I was hoping for something cheaper, though it's very possible that around $3 is the going rate. But this does add a lot to the potential price of the board.

 

A possible solution: There's actually an electronics surplus store nearby here that sells old motherboards (and lots old 486 boards had socketed SRAM for the cache.) At $1 per 486 board, you get up to 8 SRAM chips. It probably doesn't matter much that the chips were something like 32k each... just tie the upper address lines to ground. I would rather use new parts, but it's hard to argue with 12.5 cents vs. $3.

[supercat]

Just got my Digikey order in.  The SRAM has a multiplexed data/address bus, so it totally unsuitable.  I should have checked the datasheet first.  I have some spare SRAM chips from old motherboards that I will use for prototyping, but I will need to secure a better source if I am going to lay this out on a board.

973313[/snapback]

 

Out of curiosity, what sort of SRAM has a multiplexed address/data bus? Especially one that size?

[CPUWIZ]

Does anyone know a good, cheap SRAM chip?  It doesn't matter how big the SRAM chips are, only that they must be DIP or PLCC.  I can't work with surface mount stuff.

973313[/snapback]

 

Not sure what you consider cheap.

 

http://www.jdr.com/interact/item.asp?itemno=gr-staticram

973317[/snapback]

Hmm. I was hoping for something cheaper, though it's very possible that around $3 is the going rate. But this does add a lot to the potential price of the board.

 

A possible solution: There's actually an electronics surplus store nearby here that sells old motherboards (and lots old 486 boards had socketed SRAM for the cache.) At $1 per 486 board, you get up to 8 SRAM chips. It probably doesn't matter much that the chips were something like 32k each... just tie the upper address lines to ground. I would rather use new parts, but it's hard to argue with 12.5 cents vs. $3.

973340[/snapback]

 

Very true, but lots of 486 boards also have bad RAM by now, not sure if the time invested in testing them all would be worth it to me.

[djmips]

Very true, but lots of 486 boards also have bad RAM by now, not sure if the time invested in testing them all would be worth it to me. 

973346[/snapback]

 

Just curious, do you have experience that the SRAM going bad?

 

I've had good experience with old SRAM myself.

 

In any case, a RAM tester wouldn't be too hard to rig up, if you wanted to do it. A ZIF socket and a micro running a ram test algorithm.

 

EDIT - Just wanted to post something 6502 and memory test related. This is from 6502.org, a RAM test snippet for finding faulty address lines.

 

RAM TEST

Edited November 29, 2005 by djmips

[CPUWIZ]

Very true, but lots of 486 boards also have bad RAM by now, not sure if the time invested in testing them all would be worth it to me. 

973346[/snapback]

 

Just curious, do you have experience that the SRAM going bad?

 

Sure, I had the same thought when I was messing with building a RAM cart for the 7800, "Ahh, f*ck it, I am just gonna use old 486 RAM!". Many wasted hours until I figured out that it was bad RAM.

 

But yes, you are right, if building a RAM tester is feasable for him, it would be the way to go. I would tack on the extra $2.00 or whatever to the end consumer. Time is precious, writing microcode for a RAM tester would be considered time to me.

[+batari]

Just got my Digikey order in.  The SRAM has a multiplexed data/address bus, so it totally unsuitable.  I should have checked the datasheet first.  I have some spare SRAM chips from old motherboards that I will use for prototyping, but I will need to secure a better source if I am going to lay this out on a board.

973313[/snapback]

 

Out of curiosity, what sort of SRAM has a multiplexed address/data bus? Especially one that size?

973344[/snapback]

It turns out that the chip was a real-time clock with 128 bytes of nonvolatile SRAM.

 

I found this under "SRAM" in Digikey's listing, and it showed no indication of this chip having any other function. But it was very clearly a real-time clock when I opened the package from Digikey. At first I thought the sent me the wrong part, but they didn't. This is what I get for not checking things carefully enough.

 

Interestingly, though it was obviously intended for other purposes, the chip can function as a general-purpose SRAM, and it would have been more than fast enough for the 2600 if not for the multiplexed buses.