96 replies to this topic

[ClausB]

This new thread is for developers of the video upgrade we started designing in this old thread. The development is an open collaboration, so if you have specific, valid contributions to the design, please post them here. General questions and comments should go to the old thread, please.

Edited by ClausB, Fri Oct 23, 2009 11:27 AM.

[ClausB]

Recap:

This is what I envision for Stage I, which has two banks, one for ANTIC and one for enhanced luma. It will have an 8-bit shift register, a 7.2 MHz clock, and up to 3 modes: 80 horizontal pixels of 16 brightness levels; 160 pixels of 4 levels; 320 pixels of 2 levels. Of course, these all overlay the regular ANTIC/GTIA display. The first mode is like an extra GR.9 mode. When overlaid on a GR.11 screen, 256 simultaneous colors would be available, without DLIs. The last mode is like an extra GR.8 mode.

Stage II would use three banks, a 14.3 MHz clock, and a 16-bit shift register. Possible modes are: 160 horizontal pixels of 16 brightness levels; 320 pixels of 4 levels; 640 pixels of 2 levels. The last mode could provide clear 80-column text with background colors provided by ANTIC/GTIA.

Stage III could use all four banks and a 24-bit shift register, if the Atari data bus can be switched that fast. Among its modes could be 160 horizontal pixels of 64 RGB-like colors (2 bits per R, G, and B, encoded into NTSC).

Attached Thumbnails

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[ClausB]

Some timing diagrams to chew on:

Normal ANTIC DMA Read Cycle - 559 ns
 
                                   ___________________________
Phi2  \___________________________/                           \
 
      _      __________________________________________________
A0-15 _XXXXXX__________________________________________________
 
      _                                                     ___
D0-7  _>-----------------------------------<XXXXXXXXXXXXXXXX___
 
 
 
Double (LEM Stage 1) Read Cycle
 
                                   ___________________________
Phi2  \___________________________/                           \
 
      _      ______________________ ___________________________
A0-14 _XXXXXX______________________X___________________________
                      Bank 1                   Bank 0
      _       ______________________ __________________________
D0-7  _XXXXXXX______________________X__________________________
 
 
 
Triple (LEM Stage 2) Read Cycle
 
                                   ___________________________
Phi2  \___________________________/                           \
 
      _      ______________________ _____________ _____________
A0-14 _XXXXXX______________________X_____________X_____________
                      Bank 2           Bank 1        Bank 0
      _       ______________________ _____________ ____________
D0-7  _XXXXXXX______________________X_____________X____________
 

The normal cycle has lots of dead time from when the address lines are stable to when the data lines need to be stable, because memory circuits were slow back then. ANTIC does not sample the data lines until the end of the cycle, when the Phi2 clock signal goes low. The LEM SRAM is much faster so we can squeeze more read cycles into each ANTIC cycle. The data from Banks 1 and 2 become the enhanced luma, while the Bank 0 data go to ANTIC as before.

[ClausB]

We'll concentrate here on the Stage 2 design, which should fit into a CPLD and a 128K x 8 bit SRAM.

We need at least this many flip-flops in the CPLD:

Luma data register: 16 bits (2 reads from SRAM)
Mode register: 2 bits (3 display modes plus off)
Bank select register: 4 bits (16 8K banks)
Clock multiplier: 3 bits (1.8 MHz * 8 -> 14.3 Mhz)

Total: 25 FFs

Have I forgotten anything?

[Rybags]

Can we recap on how the thing works (logically)?

Is it a case of having everything in a cart, and snooping the address bus?
So, then when we know Antic is reading what should be a video memory address, we know that we do those extra reads in the interim? Then the luma is generated and added to what's already coming out of the monitor port.

[ClausB]

It will plug into the cart slot and, with a short cable, into the audio/video connector. Its S-video connector will output the enhanced video. No need to open the Atari or solder anything. It will have 128K bytes of RAM, banked within the 8K cart space. It will assume that, while the enhanced display is active, any read from that 8K space is ANTIC DMA and it will read the SRAM and spit out luma. DLIs can enable it just before the top of the display and disable it just after the bottom, and the programmer will have to be careful not to read that 8K in the interim, lest he get sparkles.

I'm tending to favor the idea of using the right cart space ($8000-$9FFF) instead of the left space, for at least two reasons:
- The XL OS doesn't like it when you switch RAM/ROM contents above $BFF0.
- It would allow built-in BASIC to run.

[mos6507]

How would this work with player missile graphics? Would it leave them untouched?

[ClausB]

ClausB, on Fri Oct 23, 2009 11:21 AM, said:

This new thread is for developers of the video upgrade we started designing in this old thread. The development is an open collaboration, so if you have specific, valid contributions to the design, please post them here. General questions and comments should go to the old thread, please.

I answered the previous post in the old thread.

[ClausB]

ClausB, on Fri Oct 23, 2009 11:44 AM, said:

We need at least this many flip-flops in the CPLD:

Luma data register: 16 bits (2 reads from SRAM)
Mode register: 2 bits (3 display modes plus off)
Bank select register: 4 bits (16 8K banks)
Clock multiplier: 3 bits (1.8 MHz * 8 -> 14.3 Mhz)

Total: 25 FFs

We need at least this many signal pins on the CPLD:

Inputs:
8 for D0 - D7
1 for -D5xx
1 for Phi2
1 for R/-W
1 for -S4 or -S5

Outputs:
4 for SRAM A13 - A16
1 for SRAM -WE
4 for Lum0 - Lum3

Total: 21 I/O pins

What have I missed?

[ClausB]

ClausB, on Fri Oct 23, 2009 3:01 PM, said:

We need at least this many flip-flops in the CPLD:

Luma data register: 16 bits (2 reads from SRAM)
Mode register: 2 bits (3 display modes plus off)
Bank select register: 4 bits (16 8K banks)
Clock multiplier: 3 bits (1.8 MHz * 8 -> 14.3 Mhz)

Total: 25 FFs

We need at least this many signal pins on the CPLD:

Inputs:
8 for D0 - D7
1 for -D5xx
1 for Phi2
1 for R/-W
1 for -S4 or -S5

Outputs:
4 for SRAM A13 - A16
1 for SRAM -WE
4 for Lum0 - Lum3

Total: 21 I/O pins

From Atmel: "The ATF1500 has 32 I/O pins and 4 input-only pins. Each I/O pin is associated with a logic macrocell containing a flip-flop."

Here's what we need:
16 cells for data register and all 12 input pins
4 cells for bank register and 4 SRAM address pins
2 cells for mode register
1 cell and pin for SRAM -WE
4 cells and pins for Luma outputs
That's 27 cells with 21 I/O pins so far. That leaves 5 cells with 5 I/O pins plus 10 I pins for miscellany, including the clock multiplier, which is still nebulous.

So it appears the Atmel ATF1500 might work.

[candle]

cosider moving it to bigger cpld like xc95144 (144 macrocells, JTAG programmable with simple programmer) - you can get it in plcc package if you really want to (for a price though) or just an tqfp for a pennies

[bob1200xl]

I just happen to have a couple of ATF1500s lying around... ATF1504s with 64 macrocells (two per I/O pin) in a 44 pin PLCC package.

A clock mutiplier? A Phase Locked Loop? We don't need to be in phase exactly, do we? Can't we start our SRAM anytime in the first half of the cycle and just run two memory accesses back-to-back? We have 280ns to hit memory twice. Worst case on a 14mhz clock would be 70ns of skew. Plenty of time...

(I have some 28mhz oscillators, too)

Bob

ClausB, on Fri Oct 23, 2009 4:14 PM, said:

ClausB, on Fri Oct 23, 2009 3:01 PM, said:

We need at least this many flip-flops in the CPLD:

Luma data register: 16 bits (2 reads from SRAM)
Mode register: 2 bits (3 display modes plus off)
Bank select register: 4 bits (16 8K banks)
Clock multiplier: 3 bits (1.8 MHz * 8 -> 14.3 Mhz)

Total: 25 FFs

We need at least this many signal pins on the CPLD:

Inputs:
8 for D0 - D7
1 for -D5xx
1 for Phi2
1 for R/-W
1 for -S4 or -S5

Outputs:
4 for SRAM A13 - A16
1 for SRAM -WE
4 for Lum0 - Lum3

Total: 21 I/O pins

From Atmel: "The ATF1500 has 32 I/O pins and 4 input-only pins. Each I/O pin is associated with a logic macrocell containing a flip-flop."

Here's what we need:
16 cells for data register and all 12 input pins
4 cells for bank register and 4 SRAM address pins
2 cells for mode register
1 cell and pin for SRAM -WE
4 cells and pins for Luma outputs
That's 27 cells with 21 I/O pins so far. That leaves 5 cells with 5 I/O pins plus 10 I pins for miscellany, including the clock multiplier, which is still nebulous.

So it appears the Atmel ATF1500 might work.

[candle]

Bob, if You'll generate video signal with 70ns of skew it will get disorted

[Rybags]

What about Antic Refresh cycles?

Don't these output Row addresses on the bus? Or do they only go to RAM?

Is it actually possible to have a Left Cartridge that only occupies $8000-$9FFF or would you also need to replicate the Basic ROM?

[ClausB]

bob1200xl, on Fri Oct 23, 2009 5:36 PM, said:

I just happen to have a couple of ATF1500s lying around... ATF1504s with 64 macrocells (two per I/O pin) in a 44 pin PLCC package.

Perfect! Less crowded.

Quote

A clock mutiplier? A Phase Locked Loop? We don't need to be in phase exactly, do we? Can't we start our SRAM anytime in the first half of the cycle and just run two memory accesses back-to-back? We have 280ns to hit memory twice. Worst case on a 14mhz clock would be 70ns of skew. Plenty of time...

candle, on Fri Oct 23, 2009 6:09 PM, said:

Bob, if You'll generate video signal with 70ns of skew it will get disorted

I agree with you both. SRAM timing is not very critical but video clocking is. And the same clock will be used for both.

[bob1200xl]

Perhaps... if we use a 28mhz clock an sync on either phase, we can cut the skew down to 17ns. That should look OK, even on an LCD. On an analog monitor, you won't have a big enough 'pipe' to notice the edge slop, will you?

Bob

candle, on Fri Oct 23, 2009 6:09 PM, said:

Bob, if You'll generate video signal with 70ns of skew it will get disorted

[bob1200xl]

Cart select (S4,S5) is disabled on refresh cycles. Yes, you can occupy just the right cartridge by asserting the proper RDx input. Monkey Wrench does this on an 800XL.

Bob

Rybags, on Fri Oct 23, 2009 6:18 PM, said:

What about Antic Refresh cycles?

Don't these output Row addresses on the bus? Or do they only go to RAM?

Is it actually possible to have a Left Cartridge that only occupies $8000-$9FFF or would you also need to replicate the Basic ROM?

[ClausB]

Rybags, on Fri Oct 23, 2009 6:18 PM, said:

What about Antic Refresh cycles?

Don't these output Row addresses on the bus? Or do they only go to RAM?

I think we discussed that in the old thread. IIRC the XL MMU does not assert the cart select lines during refresh. It might be an issue on the 400/800, though. I'll look at it.

Quote

Is it actually possible to have a Left Cartridge that only occupies $8000-$9FFF or would you also need to replicate the Basic ROM?

Yes, the cart connector has two separate 8K select lines, -S4 and -S5. If you ignore -S5 and respond to -S4, you get $8000-$9FFF.

[ClausB]

IMO the clock multiplier is the biggest challenge here. Maybe we should look for a dedicated PLL chip instead of trying to do it in the CPLD. Once we have solid 14.3 MHz (synced to the cart's 1.8 MHz) we can divide it down in the CPLD to get states for reading the SRAM and clocking out the luma.

Edited by ClausB, Fri Oct 23, 2009 7:40 PM.

[candle]

consider using pal color clock synchronisation circuit to synchronise clock domains
14.3mhz of ntsc system is beauty (because of stock crystal value), but you won't get it working with pal units
at least working in sync

[ClausB]

candle, on Sat Oct 24, 2009 5:23 AM, said:

consider using pal color clock synchronisation circuit to synchronise clock domains
14.3mhz of ntsc system is beauty (because of stock crystal value), but you won't get it working with pal units
at least working in sync

What is the frequency of the cart connector's Phi2 signal on PAL machines? If we use a PLL or some other clock multiplier circuit to multiply Phi2's frequency by 8, then we'll have a good luma clock. We don't care about the color subcarrier frequency since this is a luma-only circuit, right?

[ClausB]

ClausB, on Sat Oct 24, 2009 6:53 AM, said:

candle, on Sat Oct 24, 2009 5:23 AM, said:

consider using pal color clock synchronisation circuit to synchronise clock domains
14.3mhz of ntsc system is beauty (because of stock crystal value), but you won't get it working with pal units
at least working in sync

What is the frequency of the cart connector's Phi2 signal on PAL machines? If we use a PLL or some other clock multiplier circuit to multiply Phi2's frequency by 8, then we'll have a good luma clock. We don't care about the color subcarrier frequency since this is a luma-only circuit, right?

According to the 800XL schematic, the PAL system clock crystal is 3.547 MHz (3.580 on NTSC). So the frequency of the cart connector's Phi2 signal is 1.77 MHz (1.79 on NTSC). If we use a PLL or some other clock multiplier circuit to multiply Phi2's frequency by 8, then we'll have a good luma clock of 14.19 MHz (14.32 on NTSC).

[bob1200xl]

OK - what's first on the agenda? Should we make some cartridge extenders? First issue is whether we want to gold-plate the contacts? Do we want it on a short cable or just lift the cart away from the test machine? I think both may be doable in one package - a dual-row header for a cable and a connector at the top, like an Fte cart. No logic involved, just wiring.

Bob

[ClausB]

bob1200xl, on Sun Oct 25, 2009 4:02 PM, said:

OK - what's first on the agenda? Should we make some cartridge extenders? First issue is whether we want to gold-plate the contacts? Do we want it on a short cable or just lift the cart away from the test machine? I think both may be doable in one package - a dual-row header for a cable and a connector at the top, like an Fte cart. No logic involved, just wiring.

Bob

FRENCH GUARD: Well, I'll ask him, but I don't think he'll be very keen. Uh, he's already got one, you see?
ARTHUR: What?
GALAHAD: He says they've already got one!
ARTHUR: Are you sure he's got one?
FRENCH GUARD: Oh, yes, it's very nice-a. (I told him we already got one.)

GET ON WITH IT!

Oh, sorry, yes, I've already got one. Its contacts are plated with, well, copper oxide.

Attached Thumbnails

• 

[bob1200xl]

yes,,, well,,, ummmm... perhaps some other collaborators would like one?

They would be useful for folks that want to mount their Atari in a PC case, also.

And, I need at least one, maybe more.

We could just jump into the LEM, if you like. A 44-pin PLCC and an SRAM. A PLL and an Op-Amp. What else?

Bob

ClausB, on Sun Oct 25, 2009 5:08 PM, said:

bob1200xl, on Sun Oct 25, 2009 4:02 PM, said:

OK - what's first on the agenda? Should we make some cartridge extenders? First issue is whether we want to gold-plate the contacts? Do we want it on a short cable or just lift the cart away from the test machine? I think both may be doable in one package - a dual-row header for a cable and a connector at the top, like an Fte cart. No logic involved, just wiring.

Bob

FRENCH GUARD: Well, I'll ask him, but I don't think he'll be very keen. Uh, he's already got one, you see?
ARTHUR: What?
GALAHAD: He says they've already got one!
ARTHUR: Are you sure he's got one?
FRENCH GUARD: Oh, yes, it's very nice-a. (I told him we already got one.)

GET ON WITH IT!

Oh, sorry, yes, I've already got one. Its contacts are plated with, well, copper oxide.