Posted Sat Jun 18, 2011 3:35 PM
Posted Thu Jun 23, 2011 3:41 AM
Ksarul, on Sat Jun 18, 2011 3:35 PM, said:
Posted Sun Oct 9, 2011 1:10 PM
Posted Sun Oct 9, 2011 3:28 PM
retroclouds, on Sun Oct 9, 2011 1:10 PM, said:
Posted Mon Oct 10, 2011 12:39 AM
OLD CS1, on Sun Oct 9, 2011 3:28 PM, said:
Posted Mon Oct 10, 2011 4:51 AM
sometimes99er, on Mon Oct 10, 2011 12:39 AM, said:
OLD CS1, on Sun Oct 9, 2011 3:28 PM, said:
Posted Mon Oct 10, 2011 11:20 AM
retroclouds, on Sun Oct 9, 2011 1:10 PM, said:
Posted Mon Oct 10, 2011 1:03 PM
rocky007, on Mon Oct 10, 2011 11:20 AM, said:
Posted Sun Oct 16, 2011 7:52 PM
Vorticon, on Mon Oct 10, 2011 1:03 PM, said:
rocky007, on Mon Oct 10, 2011 11:20 AM, said:
Posted Sun Oct 16, 2011 8:10 PM
Posted Mon Oct 17, 2011 4:26 AM
OLD CS1, on Sun Oct 16, 2011 8:10 PM, said:
Edited by retroclouds, Mon Oct 17, 2011 4:26 AM.
Posted Mon Oct 17, 2011 9:47 AM
retroclouds, on Sun Oct 9, 2011 1:10 PM, said:
Posted Mon Oct 17, 2011 3:51 PM
Posted Tue Oct 18, 2011 4:08 AM
; VDP usage
; =========
;
;
; PNT (VDP register 2)
; ---------------------
; Register 2 tells the VDP where the starting address of the Name Table is located in VRAM. The
; range of its contents is from O-F. The contents of the register form the upper four bits of
; the 14-bit VDP address, therefore making the location of the Name Table in VRAM equal to
; (Register 2) * 400 (Hex)
;
;
; CT (VDP register 3)
; -------------------
; Register 3 tells the VDP where the starting address of the Color Table is located in VRAM. The
; range of its contents is from O-FF. The contents of the register form the upper eight bits of
; the 14-bit VDP address, therefore making the. location of the Color Table in VRAM equal to
; (Register 3) * 40 (Hex) <--- Applies to graphics mode 1 only
;
;
; PDT (VDP register 4)
; --------------------
; Register 4 tells the VDP where the starting address of the Pattern Table is located in VRAM.
; The range of its contents is from 0-7. The contents of the register form the upper three bits of
; the 14 bit VDP address, therefore making the location of the Pattern Table in VRAM equal to
; (Register 4) * 800 (Hex).
;
;
; SAT (VDP register 5)
; --------------------
; Register 5 tells the VDP where the starting address of the Sprite Attribute Table is located in
; VRAM. The range of its contents is from 0-7F. The contents of the register form the upper
; seven bits of the 14 bit VDP address, therefore making the location of the Sprite Attribute
; Table in VRAM equal to (Register 5) * 80 (Hex).
;
;
; SDT (VDP register 6)
; --------------------
; Register 6 tells the VDP where the starting address of the Sprite Pattern Table is located in
; VRAM. The range of its contents is from 0-7. The contents of the register form the upper
; three bits of the 14 bit VDP address, therefore making the location of the Sprite Pattern Table
; in VRAM equal to (Register 6) * 800 (Hex).
;
;
; VRAM usage in Tutankham
; =======================
;
; Usage Memory Description Size Remarks
; ===== ============== ====================== ========== ============================
; SDT >0000 - >079F Sprite Pattern Table 2048 bytes -
; PNT >0800 - >0AFF 1st screen PNT (32*24) 768 bytes Active when FLAG2{WBIT3} = 0
; SAT >0B00 - >0B7F Sprite Attribute table 128 bytes -
; FREE >0B80 - >0BFF ***RESERVED*** 128 bytes In case we need a second SAT
; PNT >0C00 - >0EFF 2nd screen PNT (32*24) 768 bytes Active when FLAG2{WBIT3} = 1
; CT >0F00 - >0F19 Screen color table 32 bytes -
; FREE >0F20 - >0FFF ***FREE*** 196 bytes Free for future use
; PDT >1000 - >27FF Pattern descriptor table 6144 bytes The screen pattern descriptor table
; FREE >2800 - >29FF ***RESERVED*** 512 bytes This is where our sound data will go
; VSCREEN >3000 - >3FFF Magellan screen map 4096 bytes The curent level as exported by Magellan
Posted Tue Oct 18, 2011 7:09 AM
Posted Sat Mar 24, 2012 3:59 PM
Posted Sat Mar 24, 2012 7:43 PM
Posted Sun Mar 25, 2012 1:25 AM
Posted Sun Mar 25, 2012 1:08 PM
OLD CS1, on Sun Oct 16, 2011 8:10 PM, said:
REF SPCHWT, SPCHRD
;equates
PHROM Data >0000
H10 Byte >10
HAA Byte >AA
EVEN
;readit routine
; The following code segment gets copied into 16-bit RAM
; because TI states that the 8-bit bus cannot be used
; immediately after a read from the speech synth
; so we have to copy the code that reads data and does
; a delay afterwards into the 16-bit RAM, otherwise it
; would be executed from the RAM expansion, using the
; 8-bit bus!
readit movb @>9000,@>8328 ; read byte from synth into CPU RAM
src r4, 12 ; 12 microseconds delay (according to Willsy)
rt ; now 8-bit bus is free, so return
CHECK
;initialization for writing the readit routine to 16-bit RAM
li r1, >8330 ; address where to put reading code
li r2, readit ; address where to copy reading code from
li r3, 10 ; 10 bytes to copy
dr2 mov *r2+,*r1+ ; copy a word of code into CPU RAM
dect r3 ; decrement r3 by two (?!)
jh dr2 ; copy more words if necessary
; here comes the actual checking code
clr @PHROM
LOAD mov @PHROM, R0 ;Address to load
li r2, 4 ;Four nybbles to load
LOADLP
src R0, 4 ;Start with least significant nybble
mov R0, R1
src R1, 4
andi R1, >0F00 ;get only particular nybble
ori R1, >4000 ; Put in >4X00 format
movb R1, @>9400 ;Write the nybble
dec R2
jne LOADLP
li R1, >4000
movb R1, @>9400 ;Write the fifth nybble
;Delay of 42 microseconds
li R1, 10
DLY dec R1
jne DLY
movb @H10, @>9400 ;Write command for reading
src R1, 12 ;delay of 12 microseconds
bl @>8330 ;read status byte
cb @>8328,@HAA ;is it >AA?
jeq SPEAK
jne NOSPEECH
I hope this is clear enough.
Posted Tue Mar 27, 2012 11:37 AM
Willsy, on Sun Mar 25, 2012 1:25 AM, said:
Edited by retroclouds, Tue Mar 27, 2012 11:38 AM.
Posted Tue Mar 27, 2012 1:44 PM
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