29 replies to this topic

[SeaGtGruff]

I have a few questions about some things in the TIA schematics.



Question 1: What is the five-sided symbol immediately after the OSC pin? Does it represent a digital-to-analog converter?

Question 2: The signal from the OSC pin goes to inverter D (the letter D refers to a particular type of transistor, as listed on sheet 5). Then the signal from inverter D is split, with one line going to inverter A and the other line going to inverter G. But then the signal from inverter A goes to inverter G. So what comes out of inverter G?

Example:
OSC = 0, 0 -> inv.D -> 1 -> inv.G -> 0
OSC = 0, 0 -> inv.D -> 1 -> inv.A -> 0 -> inv.G -> 1
Does inverter G output 0 or 1? Or does it start at 0 and then change to 1?

Example:
OSC = 1, 1 -> inv.D -> 0 -> inv.G -> 1
OSC = 1, 1 -> inv.D -> 0 -> inv.A -> 1 -> inv.G -> 0
Does inverter G output 1 or 0? Or does it start at 1 and then change to 0?

I'm guessing the answer has something to do with (a) the signal being analog, so it isn't high or low per se; (b) the different specs for transistors A, D, and G; © propagation delay; or (d) some combination of the above-- but I can't figure out what the output of inverter G will be. This type of thing shows up all through the schematics, so I want to be sure I'm interpreting it right.



Question 3: What is the symbol between the first inverter A and the second inverter A, where the line from the D0 pin crosses the Φ2 line? I'm guessing it might be a cell; is that right? If so, what value will it store? The same goes for the second one that cross the /Φ2 line.

Thanks in advance.

Michael

[Syntaxerror999]

bump (i'd like to see this answered)

[SeaGtGruff]

SeaGtGruff, on Sun Jul 17, 2011 12:04 AM, said:

Question 3: What is the symbol between the first inverter A and the second inverter A, where the line from the D0 pin crosses the Φ2 line? I'm guessing it might be a cell; is that right? If so, what value will it store? The same goes for the second one that cross the /Φ2 line.

What I'm looking for here is a table of what the cell (if that's what it is) will hold when D0 is such-and-such and Φ2 is such-and-such. Since a cell holds a charge, I presume that if D0 is high and Φ2 is high, then the cell's value will be high. And if D0 is low and Φ2 is low, then the cell's value will be low. Is that right? And what about when one is high and the other is low?

Michael

[SeaGtGruff]

Okay, I'm still struggling to understand the schematics, and I *think* I now understand something that was puzzling me.

Look at this section of sheet 1:



This is the detail for the circuits used in the poly5 register. A similar circuit is used in the poly6 register (horizontal sync counter), except for the addition of a reset line, so that circuit's called D1R (i.e., D1 with Reset):



The part that's been confusing me is the symbol that-- according to various sources on the web-- looks like the symbol for a cell. In some places I think the schematics refer to it as a latch (e.g., on sheet 2 where it shows the data latches and address latches).

Anyway, what I'm thinking is that the extra line that comes up to the signal line without actually touching it-- usually it's a clock line, but not always-- is preventing the signal from flowing unless the extra line is high (active). Or maybe it latches on and saves the signal's state when the extra line is active, something like that. So it lets the two clocks drive the circuit by controlling when the output changes.

I'll take the poly6 counter as an example, and ignore the reset line.



This shows two "bits" or D1R circuits of the poly6 counter. Suppose the first D1R circuit has a 0 going into it. The inverter or NOT gate (see the D1R closeup) will change it to a 1, then the NOR gate will change it back to a 0 (whether or not the reset line coming in from the bottom is 1). *But* we don't want it to flow through right away, we want it to wait until it's time for the shift register to shift. So the HΦ1 line lets the 0 across when HΦ1 is active, it goes through the inverter, and comes out a 1. But then the HΦ2 line doesn't let the 1 across until HΦ2 is active, at which time it goes through the NOR gate and comes out as a 0, which then flows into the next D1R circuit. When it gets to the next D1R circuit, it's held back until HΦ1 goes high again, goes through an inverter, and is held back until HΦ2 goes high again. That way, each D1R circuit sends its output to the next D1R circuit only when HΦ2 is high, then has to wait for the next HΦ1-HΦ2 cycle to shift again.

I might not be describing the details correctly, but it seems like that must be the gist of how it works.

Now if I could just figure out how those feedback lines work.

Michael

Edited by SeaGtGruff, Sun Jul 17, 2011 11:57 PM.

[Benzman66]

If you get it figured out, maybe you could sell the deal to Brad at Best Electronics. He is always getting more parts manufactured for the Ataris.

[SeaGtGruff]

Benzman66, on Mon Jul 18, 2011 5:14 PM, said:

If you get it figured out, maybe you could sell the deal to Brad at Best Electronics. He is always getting more parts manufactured for the Ataris.

I thought other people had already figured it all out, or most of it. There are certainly numerous people far more educated and qualified than I am as far as understanding electronics and reading schematics. I don't kid myself that I'm uncovering anything that no one's ever understood before-- I just want to be able to understand the schematics for myself, even though I figure it's all old hat for other people.

Right now there are at least four things that are stumping me.

(1) I don't understand the feedback lines where signals split and go into two separate circuits, then the output of one circuit goes into the other-- like the three inverters right after the OSC pin. It's done all through the schematics, with inverters, with NOR gates, etc. I understand the concept of propagation delay, and the best I can figure is that the output starts out with one value and then quickly changes to another value because of the feedback line. I'm calling it a feedback line because the notes on sheet 2 refer to some feedback lines that were apparently removed in revision E, so I guess that's what they're called. The closest thing I can find on the web-- other than flip-flops, which are sort of similar but different-- is a picture of a tri-state driver that sort of looks like an inverter with a third line coming into the side, but it doesn't have the NOT circle at the output end of the triangle, and the description of how it works doesn't seem to make sense when applied to the TIA schematics, so I don't think it's relevant.

(2) I have trouble trying to follow the logic of the flip-flops. I understand what the output's supposed to be, according to the web descriptions of /S-/R flip-flops, but I'd like to understand what it's doing from one cycle to the next.

(3) Last week I thought I had the poly4 counter all figured out-- on the broad level, if not at the detailed level-- but then I realized that the AUDC0 lines are apparently the *opposite* of what I'd thought they were (at least, I *think* they are). That is, if you look at the AUDV0 register, the circuits for the bits are labeled with an "L," and there's a closeup of the "L" circuit design on sheet 1. Those make sense, because you've got a line from an AUDV0 bit and the line from the poly4 counter going into a NOR gate, so the only way the output of the NOR gate will be 1 is if the AUDV0 bit line and the poly4 line are both 0-- and the "L" closeup on sheet 1 clearly shows that the two lines coming out of the right side are D (top line) and /D (bottom line). For example, if AUDV0 D0 is a 1, then the bottom output line is a 0. I thought the AUDC0 register worked the same way, but the circuits don't have the "L" label on them-- which implies that they're like the AUDF0 circuits shown in the closeup in the bottom left corner of sheet 4, and *that* closeup shows the top output line as the /D line, and the bottom line as the D line. So if AUDC0 D0 is 0, the top line will be 1, and the bottom line will be 0, which doesn't seem right.

(4) And of course there are those dang circles, which have been discussed before (see the "schematic weirdness" thread from a while back). From what I understand, they're used with pull-ups or pull-downs. The address decodes on sheet 2 specifically refer to "pull-downs," but that doesn't mean they're *all* pull-downs. From what I've read on the web, it's going to depend on whether the line is connected to a power source or a ground, or (since it could be connected to both) more specifically, where the resistor and the open circuits are placed in relation to power or ground. Apparently the circles themselves represent open drains or open collectors (although I'm not sure about that), and the resistors are either pull-up resistors or pull-down resistors. All I care about is how to translate the circles on the lines into the correct equivalent logic. Last week, when I thought I had poly4 all figured out, I had concluded that only one of the vertical lines can be active at once, and it seemed to make sense-- but that was when I had the AUDC0 lines *backwards* from what they (apparently) are. Now I don't know what to think.

Last week I'd also decided-- somewhat arbitrarily-- to call the line coming out of poly4 and going to AUDV0 as "poly4_bit4," since it fits with the idea that the last bit is the output bit. But now I'm going with Q6, Q7, Q8, and Q9 as the poly4 bits, which means the output line is actually "NOT poly4_bit4," or /Q9. That fits the logic of AUDV0, where the output lines are the NOT lines. It also fits the description that poly4 is always high when AUDC0 is set to %0000-- poly4_bit4 (or Q9) is always 1, so /Q9 is always 0, which is required for the NOR gates at AUDV0 to work right.

That means the /S line of the poly4_bit1 circuit is poly4_bit0-- i.e., the value that gets shifted into poly4_bit1-- so it has to be 1 when AUDC0 is %0000. But it goes through an inverter first, so the signal going into the inverter has to always be 0, which means the open collectors and pull-up (or pull-down) resistors have to result in 0. So now I'm getting confused again, given that those AUDC0 lines are the opposite of what I'd thought they were.

What I've found is that when I'm having trouble figuring out how something works in one spot, it often helps to find another spot in the schematics that do the same thing, or at least something similar enough. Sometimes it's easier to figure it out somewhere else first-- like with those latches or cells. When I looked at the D1 and D1R circuits, it started making sense. And now it seems pretty obvious-- the value of the cell or latch gets "frozen" or saved when the second line goes high, and it keeps that value until the next time the second line goes high again, at which time it gets a new value. That also helped me realize that the circled register names don't represent the actual registers, as I'd originally thought-- they're just a signal that's active when the address latches equal the address of a particular register. I'm sure that was always obvious to some people, but I'm not an electrical engineer, and I'm trying to learn how to read the schematics on my own, so it sure wasn't obvious to me-- but now I get it.

Michael

[SeaGtGruff]

SeaGtGruff, on Mon Jul 18, 2011 9:12 PM, said:

(1) I don't understand the feedback lines where signals split and go into two separate circuits, then the output of one circuit goes into the other-- like the three inverters right after the OSC pin. It's done all through the schematics, with inverters, with NOR gates, etc. I understand the concept of propagation delay, and the best I can figure is that the output starts out with one value and then quickly changes to another value because of the feedback line. I'm calling it a feedback line because the notes on sheet 2 refer to some feedback lines that were apparently removed in revision E, so I guess that's what they're called. The closest thing I can find on the web-- other than flip-flops, which are sort of similar but different-- is a picture of a tri-state driver that sort of looks like an inverter with a third line coming into the side, but it doesn't have the NOT circle at the output end of the triangle, and the description of how it works doesn't seem to make sense when applied to the TIA schematics, so I don't think it's relevant.

I was wrong to call it a feedback line. On sheet 2 where it refers to feedback lines, it's referring to something else. Anyway, I've been looking at other places where this is done, such as on the reset line for the poly6 register (horizontal sync counter):



If we look at the detail for the D1R circuit (shown in a previous post), the reset line will have an effect only if it's 1 (since it goes into a NOR gate), so we know it should have a value of 1 if one of three situations occur-- the ERR line, RSYNL (RSYNC latch) line, or END line is active. So if we follow the logic shown in the lower left of this picture, we have something like the following:

reset = not/not not A/HΦ2
A = not B/HΦ1
B = not (ERR or RSYNL or END)

I'm using "not/not" to indicate the two inverters where one feeds into the side of the other-- the thing that's puzzling me-- and I'm using "/HΦ1" and "/HΦ2" to indicate the HΦ1 and HΦ2 "transfer devices" (which I was previously referring to as "cells" or "latches," but I realized last night that they're called "transfer devices" on sheet 2). I'll come back to those in a bit.

So if ERR = 1, or RSYNL = 1, or END = 1, then B = 0, which (as I understand it) gets "saved" by the HΦ1 transfer device when HΦ1 is active. Then A = 1, which likewise gets "saved" by the HΦ2 transfer device when HΦ2 is active. Then the reset line = not/not not 1 = not/not 0. Since the reset line can't reset poly6 unless it's 1, the result of "not/not 0" must be 1, which means the extra inverter must not have an (immediate) effect. For the moment, let's say it starts out as 1, then (after a brief propagation delay) the extra inverter changes it to 0. That works, I guess-- the 1 on the reset line makes poly6 go to 000000, then the 0 on the reset line means it will be ignored after that.

However, let's take the opposite case-- ERR = 0, RSYNL = 0, and END = 0. Then B = 1 (saved by /HΦ1), then A = 0 (saved by /HΦ2), then reset = not/not 1. So it must be 0. But if it then changes (after the propagation delay) to 1, it would reset poly6, so that doesn't seem right. The only way it makes sense is if the extra inverter is doing something else.

The description of "tri state driver" (or "three-state logic") indicates that the extra line is-- as I understand it-- an "output enable" line. If that's what this is, then the last inverter's value will be valid if the output enable line is 1, but will be ignored if the output enable line is 0. That makes more sense-- the last inverter may send out a 0 over the reset line before the propagation delay, but then the extra inverter will cause the reset line to be ignored after that. Except if that's the case, then I don't see the need for the extra inverter at all. So I'm still confused, except I've pretty much concluded that the extra inverter can't be changing the reset line from 1 to 0, or from 0 to 1, after the propagation delay. It seems like the best thing to do is just ignore the extra inverter, except I'm pretty sure Atari wouldn't have included it unless it does *something*.

As for those "transfer devices," a search for that term turned up a Wikipedia article about "charge-coupled devices," which includes the following remarks-- "A description of how the device could be used as a shift register... was described in this first entry.... The initial paper... listed possible uses as a memory, a delay line, ...." It seems to me that they're being used for all three of these purposes in the TIA-- as a memory (or "cell") to save the 0 or 1 state of a line whenever the other line (typically a clock line or register signal line) is active, and to hold back or delay the signal from proceeding further until the next transfer device goes active, and therefore to save and then shift the value in each "bit" of a shift register.

Michael

[supercat]

The TIA is implemented with NMOS technology, meaning everything is built from one style of transistor: a Negative-channel Metal Oxide Semiconductor Field Effect Transistor (also called an N-channel MOSFET or NFET). An NFET has three terminals: the source and drain, which are in this context interchangeable (typically the side closer to VDD will be labeled the source, and the other end the drain; power NFETs are generally constructed asymmetrically, and the distinction is important, but within a chip like the TIA it doesn't matter), and the gate. An NFET will connect the source and drain ends whenever the gate is 1-2 volts more positive than the less-positive end, and behave as an insulator otherwise. Note that while the voltage on the gate connects or disconnects the source and drain from each other, almost no current flows into or out of the gate itself. Note also that if one end (e.g. the source) of the MOSFET is ground and the gate is high, the MOSFET will strongly connect the other end to ground, but if the drain is tied to VDD and the gate is also at VDD, it will only pull the source weakly (as the source is pulled toward VDD, the voltage difference between the gate and source will drop so the transistor will start conducting less well).

An NMOS inverter consists of an NFET to ground and a resistor to VDD. A NAND gate consists of two NFETS in series connected to ground, along with a resistor to VDD. A NOR gate consists of two NFETs in parallel connected to ground, along with a resistor to VDD.

The D1 block consists of two inverters (each of which is a transistor to ground and a resistor to VDD), along with two discrete transistors. When the gate of a discrete transistor is high, it will act as a closed switch (though it is more effective at passing logic '0's than logic '1's). When the gate is low, it will act as an open switch. Because very little current flows into or out of a MOSFET gate, opening the switch connected to the MOSFET gate will cause the gate to simply remain in whatever state it's in, at least for awhile. Effectively, the transistor and inverter form a crude latch. Such a latching circuit is much smaller and simpler than a more 'conventional' latch using a couple of NOR gates (four transistors) but it has the disadvantage of only holding information for a few dozen microseconds. If you look in the TIA design, though, you'll notice that in all the places such latching circuits are used they'll be strobed pretty frequently, typically using a non-overlapping two-phase clock.

[SeaGtGruff]

Thank you for the input, supercat!!! Most of that went *way* over my head, but it gives me a direction to look in for trying to understand it all better, which is exactly what I needed.

I'd already just determined that in the D1, D1R, and D2 circuits-- or maybe "devices" is a better term, since they're made up of circuits themselves-- the "D" stands for "delay"; and as I'd already figured out, "1" means it has 1 input, "2" means it has 2 inputs, and "R" means it also includes a "reset" line. Since the output is always the same as the input (except if a reset line is included, in which case the output will always be 0 if the reset line is active), and since the latches inside the D1/D2/D1R devices are clock-driven, they delay the input signal by one clock cycle. And since they're driven by clock 1 and clock 2-- which could be HΦ1 and HΦ2, or AΦ1 and AΦ2, or TΦ1 and TΦ2, or even /Φ2 (Φ1) and Φ2-- their output changes (or stays the same, as the case may be) on each clock 2 signal.

Regarding the latches or "transfer devices" and how long they'll retain their state, that helps me understand why some of the devices (or collections of circuits) include a latch for the "not signal." In particular, I'm talking about the latches for the TIA registers. When the register signal line (which indicates the address bus currently holds the address of that register) is active, the first latch in each "register bit" will save the state of the data signal line that feeds into it (D0, or D1, or D2, etc.). But then the value of that latch branches off to another latch that's driven by-- or coupled with-- what I'll call the "not register" signal line (i.e., the inversion of the register signal line). So that lets the register retain the value of that particular bit once the address bus no longer holds the address of that register, since the "not register" signal line will stay active until the next time the register is written to. Thus, the register won't lose its value after a few dozen microseconds. Cool!

I'm sure you already knew that, but I'm struggling to learn it all bit by bit (no pun intended).

I *still* don't understand the purpose of the "output enable" lines (if that's what they are) that feed into some of the inverters and NOR gates, since it seems like we can just ignore them and things still make sense (and actually seem to make better sense to me if we *do* ignore them), but I hope to grasp it someday.

I might note that there are some places in the TIA schematics where there are notes referring to lines or circuits or devices that were removed in later revisions, so apparently it *was* possible to remove certain things without affecting the results. Likewise with the schematics for the CX2600 and CX2600A-- there are some places (e.g., the circuitry between the piezoelectric crystal and TIA pin 11) where things were simplified from the CX2600 to the CX2600A. I suppose the original design reflected everything Atari thought was necessary, or might be necessary, including circuits that were possibly redundant or irrelevant (just to be on the safe side). And then as time went by, and it became clear to Atari that the 2600 wasn't going to go away anytime soon after the release of its handful of "target" (originally intended) games, they were able to spend more time on looking for ways to simplify the circuitry and save a few cents here and there-- especially since a few cents, multiplied by several thousand (or hundred thousand) units, adds up to a substantial amount of money.

Again, thank you for your input!

Michael

[yllawwally]

For question 1, that looks like a buffer. Often times they are put after oscillators to clean up the signal, and to prevent interference from making the frequency shift. You were almost right however, but it's more of a analogue to digital converter.
For question 2, The output at G is High then Float, repeatedly. You can see why they need to float when you look at the divide by three circuit, which needs to feedback into the input. If this wasn't a tri-state device, it wouldn't last very long before burning out.

[SeaGtGruff]

yllawwally, on Wed Jul 20, 2011 8:47 AM, said:

For question 1, that looks like a buffer. Often times they are put after oscillators to clean up the signal, and to prevent interference from making the frequency shift. You were almost right however, but it's more of a analogue to digital converter.

Thank you, yllawwally! The closest schematic symbol I could find on the web was a DAC or ADC, and based on the direction it was pointing I thought it might be a DAC. This symbol appears to be used on *all* lines coming from an input pin.

yllawwally, on Wed Jul 20, 2011 8:47 AM, said:

For question 2, The output at G is High then Float, repeatedly. You can see why they need to float when you look at the divide by three circuit, which needs to feedback into the input. If this wasn't a tri-state device, it wouldn't last very long before burning out.

As I understand it, a tri-state circuit has three possible states-- 1, 0, or float-- so in this case, since the enable line is another inverter with identical input (or, in other places, another NOR gate with identical inputs), there are only two states-- 1 or float. Can I pretend that the float is a 0 when I'm reading any circuits that the line goes into, or should I interpret the float state as "ignore this line completely for the moment"?

Michael

[yllawwally]

For this portion of the circuit, the float is used because that line will be overriden by another gate. So ignore what's comming out of that gate, because something else will probably be controlling the line. Normally I would consider float to be a low or 0, if nothing else seemed to be controlling the line. If you look at the right hand side of the Divide by 3 section, you can see it's feeding back into that point, which is why they had to use a tri-state device.

[supercat]

A normal NMOS inverter contains a single transistor which pulls the output low whenever the input is high, and a passive pullup resistor which tries to pull the output high always, and succeeds when the transistor doesn't overpower it. NMOS design using such simple gates involves a tradeoff between using a low-value resistor, which will waste a lot of power, dissipate a lot of heat, and require a pull-down transistor strong enough to overpower it, or else using a high-value resistor which can't pull the output very fast. I believe that the side wire on a gate isn't a normal 3-state control, but rather operates a transistor in series with the high-side resistor (which can then be much smaller). Note that if the 'side' wire and the input were both high simultaneously, the gate would draw substantial additional current, since the pull-up transistor's efforts to pull the line high would be much stronger than those of a passive pull-up resistor. One should note that while pull-up transistors can switch more current than pull-up resistors when their outputs are far below their gates, NMOS pull-up transistors get very wimpy when the output voltage approaches the gate voltage. Still, since most NMOS gates will switch at voltages more than two volts below VDD, it's possible to construct a reasonably powerful signal driver by using a small gate to drive a pull-up transistor output for a much larger gate. For signals like Clk which are distributed throughout much of the chip, this is important.

[supercat]

Here's what I think is going on with the schematic at the top of the page. The clock signal will have to drive a lot of stuff on the chip, so it uses the indicated circuit to drive it strongly high and low. Note that the big bold resistor is probably as low a value as the engineers could practically produce, but the diffusion material has a non-trivial amount of resistance no matter what one does.

Attached Thumbnails

• 

[SeaGtGruff]

supercat, on Wed Jul 20, 2011 5:12 PM, said:

I believe that the side wire on a gate isn't a normal 3-state control, but rather operates a transistor in series with the high-side resistor (which can then be much smaller). Note that if the 'side' wire and the input were both high simultaneously, the gate would draw substantial additional current, since the pull-up transistor's efforts to pull the line high would be much stronger than those of a passive pull-up resistor.

This was actually one of my earlier thoughts-- that the extra inverter feeding into the side might be boosting or adding to the signal in some way (if that's what you're suggesting). My main reason for wondering that were the different transistor sizes used, although I don't understand what effect they have. I actually downloaded and installed the LTspice program a month or two ago, with the intention of replicating the schematics as best I could-- at least in sections, but (hopefully) eventually in their entirety-- then running it to see what the results were. I actually set up the OSC inverters and divide-by-three section, but when I ran it, all I could get were error messages, and I couldn't figure out how to resolve the errors. I think the main problem was that I don't understand how to define the parameters for each inverter and the other gates using the information in the transistor sizes table on sheet 5. So I gave up on trying to use LTspice for now, but maybe one day I'll learn enough to try again.

Anyway, I can follow a good deal of the schematics as long as I don't get too hung up on the details. For example, I have some trouble following the internal flow of the flip-flop circuits on a cycle-by-cycle basis, but from reading about /S-/R flip-flops I do know what the Q and /Q outputs will be, so I can follow what the poly4 register is doing. And I've been able to see how the divide-by-15 logic works (as it's called in the TIA hardware manual), as well as the divide-by-three logic, and how the poly4 clock changes based on the AUDC settings.

The so-called divide-by-15 is based on the poly5 register, with the clock that goes to the poly4 register changing whenever the poly5 register reaches 0001x (i.e., either 00010 or 00011), which occurs at intervals of 13 and 18. And from what I've seen in the actual recording I made from my heavy-sixer, it appears that multiplying the period (or dividing the frequency) doesn't double or triple these intervals as you might expect (i.e., 26 and 36, or 39 and 54, etc.). Rather, it appears that the difference between the longer and shorter intervals is always 5 (e.g., 44 and 49 rather than 39 and 54-- or 13+18+13 and 18+13+18). That would be for an odd divider. I'll have to go back and double-check, but I think even dividers may give equal intervals (i.e., 13+18 and 13+18).

The divide-by-three is accomplished by the poly4 register, which has its logic changed to produce the following sequence:

0001
1000
1100
1110
0111
0011
0001
etc.

And the divide-by-two is also accomplished by the poly4 register, which has its logic changed to produce the following sequence:

0101
1010
0101
1010
etc.

As for the base 31400 Hz frequency created by the two audio clocks, the division is actually 28-29 horizontal counts, or 112-116 color clocks-- the intervals between the audio clock 2 pulses. The audio clock 1 pulses don't have anything to do with the frequency, but they're needed to help drive the poly5 register (after the audio clocks are converted into the "tone clocks" by the audio frequency divider). There's no reason why the audio clock 1 pulses must be generated by the END and LRHB signals-- they could just as easily have been generated by any of the other counts between RHS and CNT, such as SHS and RCB. The only reason I can think of for why END and LRHB were chosen is because they create a nice pattern of intervals-- 9, 10, 18, 20-- with the second pair of intervals being double the first pair.

Michael

Edited by SeaGtGruff, Wed Jul 20, 2011 8:32 PM.

[supercat]

SeaGtGruff, on Wed Jul 20, 2011 8:29 PM, said:

This was actually one of my earlier thoughts-- that the extra inverter feeding into the side might be boosting or adding to the signal in some way (if that's what you're suggesting). My main reason for wondering that were the different transistor sizes used, although I don't understand what effect they have.

To understand transistor sizes, first understand that current in amps is the number of coulombs of electrons per second; capacitance in farads is the number of coulombs of electrons that will be required to produce a volt of back pressure. Transistor gates have a certain amount of capacitance, and they must reach a certain voltage to switch; that means they must have a certain number of electrons flow into or out of the gate. If the current flowing into or out of the gate is low, it may take awhile for enough electrons to flow to switch the transistor.

Bigger transistors will allow more current to flow when they're turned on, but they will also have higher gate capacitance than smaller transistors.

[SeaGtGruff]

I was studying the audio frequency divider and got stumped by the details of the "up counter," so I took a break and started looking at other things in the schematics. It's fun now that I at least know enough to figure out some of the things that had puzzled me before.

I decided to start with VSYNC, since it's the first (i.e., lowest-numbered) register in the TIA. Of course, I already knew the gist of what VSYNC does. But it's nice to finally be able to decipher the details for myself. VSYNC affects only two things-- the COMP SYNC (CS) signal that's output through the [SYN] pin, and the COLOR BURST (CB) signal. In turn, VSYNC is affected by only one thing-- the HORIZONTAL SYNC (HS) signal. (Well, technically it's the CS signal that's affected, not the VS signal.) As long as VSYNC is turned off, the CS, HS, and CB signals operate normally. But when VSYNC is turned on, the CB signal is disabled, and the CS signal is inverted from its normal operation-- it will be turned off during the HS period, and turned on for the rest of the scan line. Also, the CB signal gets turned on automatically after the RHS (RESET HORIZONTAL SYNC) signal. So the two types of scan lines are as follows:

With VSYNC turned off:
CC 000 -- HBLANK gets turned on
CC 020 -- CSYNC (i.e., HSYNC) gets turned on
CC 036 -- CSYNC (HSYNC) gets turned off, and CBURST gets turned on
CC 052 -- CBURST gets turned off
CC 068 -- HBLANK gets turned off (assuming HMOVE isn't latched on)

With VSYNC turned on:
CC ??? -- CSYNC gets turned on (depending on when VSYNC is written to)
CC 020 -- CSYNC gets turned off
CC 036 -- CSYNC gets turned on again

Unlike a standard NTSC or PAL "VSYNC" line, the TIA's VSYNC line isn't in the form of a serrated pulse-- i.e., it isn't turned off briefly halfway through the line, but stays on during the entire line, except for the portion of the line when HSYNC would otherwise be on.

Getting back to the audio frequency divider, the bits of the AUDF0 (or AUDF1) register are inverted-- e.g., if you write %00111 to AUDF0, the bits will be stored in the register that way, but will be inverted before they're moved into the up counter, so the up counter will start at %11000 and count up from there. I think the signal coming out of the audio frequency divider will always be 0 if any of the counter's bits are 0, and then goes to 1 when the counter reaches %11111. When the output signal goes to 1, audio clock 2 will generate the tone clock 2 signal, then audio clock 1 will generate the tone clock 1 signal. Finally, the 1 is fed back into the audio frequency divider, resetting it back to the (inverted) starting value so the counter can start counting up again. At least, that's how I think it works.

For example, if you set AUDF0 to %00000, the up counter will be initialized to %11111, and will always output a 1, since it keeps getting reset to %11111.

If you set AUDF0 to %00001, the up counter will count from %11110 to %11111, then reset to %11110 and count up to %11111, so the output will be 0, 1, 0, 1, 0, 1, etc.

If you set AUDF0 to %00010, the up counter will count %11101, %11110, %11111, %11101, %11110, %11111, etc., outputting 0, 0, 1, 0, 0, 1, etc.

And so on and so forth.

The part I'm having trouble with is understanding the details of how each bit inside the up counter interacts with the other bits, as well as the details of how the bits are reset to their starting values. I mean, I see the lines connecting the bits, but that isn't the same thing as understanding what they're doing.

One thing that puzzles me is the line that goes into bit 0 of the up counter, which looks like it's connected to a ground (the circle with a plus inside it). Doesn't that mean the line will always be low (0)? The line goes into a NOR gate, but it also gets inverted and goes into another NOR gate just below the first one. So wouldn't the bottom NOR gate always output a 0? Then the output of the bottom NOR gate goes into the next bit of the up counter, and so on. So wouldn't the bottom NOR gate of each bit always output a 0? But if that's correct, then what's the point of having the feedback line go into the bottom NOR gate as well? Evidently I'm not understanding how that line works, and it's keeping me from understanding the rest of what's happening.

Michael

Edited by SeaGtGruff, Fri Jul 22, 2011 9:22 PM.

[SeaGtGruff]

I may have answered my own question. I take it that the circle with the plus inside is a symbol for a power source, not ground? (The traditional symbol for Earth is-- you guessed it-- a circle with a plus inside.) Sheeze, it's a good thing I'm not playing with real components if I can't tell the difference between ground and a power supply!

Assuming it's a power source, things start making much more sense. The top NOR of bit 0 will always output 0, but the bottom NOR will alternate between 1 and 0, so the signal that goes to the next bit will alternate.

Michael

[SeaGtGruff]

Okay, after some sleep, I was able to get the up-counter worked out. Since I wasn't sure about the reset, I decided to pick a value of AUDF that would take several counts before it would need to reset, and began with a value that was halfway through the count, then went from there.

As best as I can figure, the reset occurs when the counter reaches 0-- as Eric Ball had said in his blog entry. I'd had trouble wrapping my head around that, because I didn't see how the counter could even count to 0-- not how it could possibly do so, because obviously it can count to any 5-bit value; but rather, how the division could work the way it does if the counter is ever *allowed* to reach 0. For example, if you set AUDF0 to %00000, the counter gets initialized to %11111 (the inversion of AUDF0), so wouldn't counting to 0 make it *two* counts instead of one (i.e., %11111, then %00000, then %11111 again, etc.)? But I was getting confused between the counter's "before" value and its "after" value, hence it seemed to me that the output of 1-- as well as the reset-- had to be occurring when the counter reaches %11111.

Another thing that was stumping me was how the reset line that feeds back into the counter works, because if it feeds a 1 back into the last NOR of every bit, that bit goes to 0. But it does this at the same time that the counter is already at 0 anyway-- or rather, a little later, since the counter is clocked by audio clock 1 and audio clock 2. Anyway, the counter's output goes to 1 when all of the values on the left side of the counter go to 0, so that first line on the left is a NOR with a pull-up resister. Once the counter is reset, the output goes back to 0 until the counter hits 0 again. So taking the first several values of AUDF0 as examples, the counter will have the following values:

AUDF0 = %00000 -> inverted to %11111
%11111 + 1 = %00000 -> output 1, then reset
%11111 + 1 = %00000 -> output 1, then reset

AUDF0 = %00001 -> inverted to %11110
%11110 + 1 = %11111 -> output 0
%11111 + 1 = %00000 -> output 1, then reset
%11110 + 1 = %11111 -> output 0
%11111 + 1 = %00000 -> output 1, then reset

AUDF0 = %00010 -> inverted to %11101
%11101 + 1 = %11110 -> output 0
%11110 + 1 = %11111 -> output 0
%11111 + 1 = %00000 -> output 1, then reset
%11101 + 1 = %11110 -> output 0
%11110 + 1 = %11111 -> output 0
%11111 + 1 = %00000 -> output 1, then reset

AUDF0 = %00011 -> inverted to %11100
%11100 + 1 = %11101 -> output 0
%11101 + 1 = %11110 -> output 0
%11110 + 1 = %11111 -> output 0
%11111 + 1 = %00000 -> output 1, then reset
%11100 + 1 = %11101 -> output 0
%11101 + 1 = %11110 -> output 0
%11110 + 1 = %11111 -> output 0
%11111 + 1 = %00000 -> output 1, then reset

etc.

Michael

[ijor]

I've just seen this thread. I'm afraid I'm leaving in a few minutes. So I can't read and answer everything (that I know the answer, of course). But a quick reply in the meantime.

SeaGtGruff, on Sun Jul 17, 2011 12:04 AM, said:

Question 2: The signal from the OSC pin goes to inverter D (the letter D refers to a particular type of transistor, as listed on sheet 5). Then the signal from inverter D is split, with one line going to inverter A and the other line going to inverter G. But then the signal from inverter A goes to inverter G. So what comes out of inverter G?

This (transistors A and G) is an NMOS Super Inverter, or an NMOS inverting Super Buffer. These circuits just affect the power and timing behaviour, they don't alter the digital functionality. You can ignore, for most purposes, whatever is present in the alternate path of this circuit (in this case, the A inverter), and treat it as a regular inverter. It is after all, just an inverter but faster, which is needed for driving big fanouts.

Edit: Made a mistake in the transistor letters. Corrected.

Edited by ijor, Sat Jul 23, 2011 5:40 PM.

[SeaGtGruff]

ijor, on Sat Jul 23, 2011 5:34 PM, said:

I've just seen this thread. I'm afraid I'm leaving in a few minutes. So I can't read and answer everything (that I know the answer, of course). But a quick reply in the meantime.

Thank you! By looking at the horizontal sync counter's reset logic, I'd already figured out on my own that I could basically just ignore the extra inverter (or, in the case of the "divide by four" logic that generates the horizontal clocks, the extra NOR gate). And yllawwally and supercat have also provided helpful comments. But every additional piece of information helps me understand it all better. I know other people (e.g., Adam Wozniak) must have figured out all of the TIA schematics years ago, but I haven't been able to find any detailed documentation of their findings, aside from a few comments about specific functions (e.g., the polynomial counters). And it seems like some things that were "documented" are really just speculation, possibly from before the TIA schematics became available for study (e.g., Ron Fries' description of the TIA sound generation, in which he suggested that the "divide by three" function of AUDC values 12, 13, 14, and 15 were achieved by using the 3.58 MHz pixel clock rate instead of the 1.19 MHz CPU clock rate, which we've since discovered to be incorrect). Andrew Towers' "TIA Hardware Notes" is closest to being a detailed document, but doesn't cover the entire TIA. Someday I'd like to document everything I can-- at least, to whatever extent I can understand it-- for the benefit of anyone else who's interested. I've already learned the answers to some questions I'd long had, such as what the signal on a VSYNC scan line *really* looks like. Thanks again, and I look forward to any additional information you can give.

Michael

[ijor]

SeaGtGruff, on Sat Jul 23, 2011 7:15 PM, said:

Someday I'd like to document everything I can

I'm afraid I can't help too much at that level. My knowledge about TIA and the 2600 is close to nothing. I used Atari computers, not consoles. But I reverse engineered the 8-bit chipset, in some cases comparing them with the schematics. So I'm quite familiar reading and understanding NMOS schematics. Is at that level that I can help. Not at the higher level which requires functional knowledge of TIA.

Please forgive if I'm repeating something that was already said...

Quote

What is the five-sided symbol immediately after the OSC pin?

Nothing special, you can ignore it. It signals an input pin with ESD protection, usually just a small resistance and a diode.

Quote

Question 3: What is the symbol between the first inverter A and the second inverter A, where the line from the D0 pin crosses the Φ2 line? I'm guessing it might be a cell; is that right? If so, what value will it store? The same goes for the second one that cross the /Φ2 line.

They are pass transistors. The two pass transistors here, each one controlled by the opposite phase of the clock, provide clock synchronization.

Quote

Anyway, what I'm thinking is that the extra line that comes up to the signal line without actually touching it-- usually it's a clock line...

It is the gate of the pass transistor. The logical value of that signal controls if the pass transistors is open or closed.

Quote

And of course there are those dang circles,

Sorry, I don't know what circles you mean. Can you point some expamle in the schematics? Do you mean the circles at the PLAs?

Quote

I *still* don't understand the purpose of the "output enable" lines...

I understand that at this point you already figured out they are not output enable lines. They are the control signal for the pullup transistor in Super Buffer gates. This is NMOS depletion load logic. Normally, gates have a non-switched pullup. This pullup consists of a depletion load transistor connecting the output of the gate to the power source, and the control is tied to the output (this is known as the gate-to-source contact). The transistor is always on (connecting source and drain), because the special characteristic of depletion load. Super buffers omit that gate to source contact. The gate is specifically driven by logic, usually the inverted value of the input. So those lines reaching the middle of the symbol, means they control the gate of the pullup.

Quote

For example, I have some trouble following the internal flow of the flip-flop circuits on a cycle-by-cycle basis...

I suggest you find some article about synchronization using two phase non-overlapping clock. This is how synchronization is implented on most NMOS devices. One consequence of this is that you must think in term of phases (half cycle) and not just whole cycles. Also take in mind that these devices use a lot of async logic.

[supercat]

SeaGtGruff, on Sat Jul 23, 2011 4:51 PM, said:

As best as I can figure, the reset occurs when the counter reaches 0

The counters reset when they reach the programmed count value. The left set of boxes is the AUDFx register, each bit of which is equipped with inverted and non-inverted outputs. Each stage of the counter is likewise equipped with inverted and non-inverted outputs. The leftmost vertical line through the larger, right-side, set of boxes, will be pulled to ground if any counter bit disagrees with its corresponding AUDFx bit. That signal is delayed by two pass gates and then fed vertically, between the two clock wires, as one of the three-inputs to a NOR gate to clear all the counter stages.

Incidentally, in the places where you see a grid of wires with circles at some of the intersection, each circle is a transistor. The gate will generally be the horizontal wire and the drain will be the vertical wire. The source will be connected to ground (as with other gates, the ground connection is not explicitly drawn). The simplest way to think about such grids is that a column will be pulled down if row where it has a circle is high. This style of logic requires the same amount of space whether all the intersections have circles or none of them do. On the other hand, such grids can be laid out very compactly. Something like the collision-detect logic uses a 30 transistors in a 5x15 grid to detect collisions. Even though 75 transistors could fit in the space that's used for 30, trying to individually wire the 30 transistors would likely use more space than putting them in the grid.

[SeaGtGruff]

ijor, on Sat Jul 23, 2011 8:56 PM, said:

SeaGtGruff, on Sat Jul 23, 2011 7:15 PM, said:

What is the five-sided symbol immediately after the OSC pin?

Nothing special, you can ignore it. It signals an input pin with ESD protection, usually just a small resistance and a diode.

So that explains why there's one immediately after every input pin.

ijor, on Sat Jul 23, 2011 8:56 PM, said:

SeaGtGruff, on Sat Jul 23, 2011 7:15 PM, said:

Question 3: What is the symbol between the first inverter A and the second inverter A, where the line from the D0 pin crosses the Φ2 line? I'm guessing it might be a cell; is that right? If so, what value will it store? The same goes for the second one that cross the /Φ2 line.

They are pass transistors. The two pass transistors here, each one controlled by the opposite phase of the clock, provide clock synchronization.

I found on sheet 2 where they're called "transfer devices" in a couple of the notes, but it's good to know their "proper" name!

ijor, on Sat Jul 23, 2011 8:56 PM, said:

SeaGtGruff, on Sat Jul 23, 2011 7:15 PM, said:

And of course there are those dang circles,

Sorry, I don't know what circles you mean. Can you point some expamle in the schematics? Do you mean the circles at the PLAs?

If by PLAs (programmable logic arrays?) you mean the grid of horizontal and vertical lines shown below the 6-bit LFSR (horizontal sync counter)-- shown in a previous post-- then yes, those are the circles I meant. They're also shown in the address decode section and collision detection section on sheet 2, as well as in the audio control section on sheet 4. I understand how they work in most of those places-- like a NOR-- and that they're used with pull-up or pull-down resistors. In supercat's reply, he says they're transistors, and a pair of explanatory comments in the address decode section on sheet 2 calls them "pull-downs," but I didn't know if they had another name (like "open collector"?).

As I said, I already understand the gist of how they work in most places. The specific place where I'm still having a little trouble is the audio control section on sheet 4. The problem I'm having there is that I *thought* I'd figured them out just fine, but then I realized that the circles apparently have the opposite values from what I'd thought-- unless the person(s) drawing the schematics didn't label the boxes correctly for the audio control register. What I mean is, the boxes for the audio volume register have an "L" on them, and the detail for the "L" ("latch") boxes are shown on sheet 1, with the top line being the normal output and the bottom line being the inverted output-- e.g., if the D0 signal is the input, then the top output is D0 and the bottom output is /D0. In other places in the schematics, they always label the boxes with an "L" so you know what they are. But in the audio frequency register, the boxes have no label, and the detail given below shows that the top line in the inverted output, and the bottom line is the normal output-- so if the D0 signal is the input, then the top output is /D0 and the bottom output is D0. Since the boxes for the audio control register don't have an "L" on them, I'm forced to conclude that either (1) they're like the audio frequency register, with the top line being the inverted output-- which throws a monkey wrench in the way I thought the circles in that section work-- or (2) they're like the audio volume register, with the bottom line being the inverted output-- in which case, the circles in that section work like I thought, the same way they do everywhere else-- but the person(s) drawing the schematic forgot to write "L" in the boxes (which seems like a pretty glaring oversight, since they're clearly labeled everywhere else). I'll provide pictures of what I mean in a separate post.

ijor, on Sat Jul 23, 2011 8:56 PM, said:

SeaGtGruff, on Sat Jul 23, 2011 7:15 PM, said:

For example, I have some trouble following the internal flow of the flip-flop circuits on a cycle-by-cycle basis...

I suggest you find some article about synchronization using two phase non-overlapping clock. This is how synchronization is implented on most NMOS devices. One consequence of this is that you must think in term of phases (half cycle) and not just whole cycles. Also take in mind that these devices use a lot of async logic.

I've watched an animated GIF of a simple flip-flop in Wikipedia, which helped a great deal, and the description of the /S-/R flip-flip also helped-- the Q output is the opposite of /S, and /Q is the opposite of Q-- so that let me follow the flow of 0s and 1s going into and out of the /S-/R flip-flops of the 4-bit LFSR used in the audio tone generator (or "audio noise generator" as they call it). But I was getting lost when I tried to follow the internal workings of the /S-/R flip-flops, even breaking it down into half cycles. I haven't tried again lately, but it's on my to-do list!

Michael

[SeaGtGruff]

supercat, on Sat Jul 23, 2011 11:59 PM, said:

SeaGtGruff, on Sat Jul 23, 2011 4:51 PM, said:

As best as I can figure, the reset occurs when the counter reaches 0

The counters reset when they reach the programmed count value. The left set of boxes is the AUDFx register, each bit of which is equipped with inverted and non-inverted outputs. Each stage of the counter is likewise equipped with inverted and non-inverted outputs. The leftmost vertical line through the larger, right-side, set of boxes, will be pulled to ground if any counter bit disagrees with its corresponding AUDFx bit. That signal is delayed by two pass gates and then fed vertically, between the two clock wires, as one of the three-inputs to a NOR gate to clear all the counter stages.

It sounds like I need to work through my example again to be sure I got/get it right!

By the way, I was looking at the address decode section to be sure I'd understood everything correctly, because I was confused that the phase 2 clock line isn't inverted before going to the address decode grid. But then I realized that the register signals don't go high until the phase 2 clock goes low, presumably so the register signals don't go high until *after* the TIA has latched the bits of the data bus and address bus.

Michael