12 replies to this topic

[Sdw]

I've been experimenting with different bankswitching methods, and looking into to those that include extra RAM as well.
One thing I've noticed is that RAM always is split into separate read/write area, for example the 256 byte area you get with CBS-cart has read from $1100-$11ff and write from $1000-$10ff.
This seems to wase adress-space, as 512 locations are used to access 256 bytes.
I'm guessing this split with separate read/write areas is due to some kind of limitation to how the 6507 adresses memory?

Another thing I've been thinking about, if I understand things correctly, 6507 only has 12-bit adressing, meaning it can adress $000-$fff.
However, how does it differentiate when adressing for example the $80-$ff area that it should go to cartridge or to built in 128-byte RAM?

[SeaGtGruff]

Sdw, on Wed Nov 23, 2011 8:48 AM, said:

I've been experimenting with different bankswitching methods, and looking into to those that include extra RAM as well.
One thing I've noticed is that RAM always is split into separate read/write area, for example the 256 byte area you get with CBS-cart has read from $1100-$11ff and write from $1000-$10ff.
This seems to wase adress-space, as 512 locations are used to access 256 bytes.
I'm guessing this split with separate read/write areas is due to some kind of limitation to how the 6507 adresses memory?

No, it's nothing to do with the 6507. I don't really know/fathom the reasons, but as I understand it, I think it's partly due to the type of RAM used, and presumably also something about how the 2600 handles I/O. It has been verified that the same read/write addresses cannot be used with the Atari Superchip-- although I believe they do work if you are emulating the Superchip with a Harmony cart. And I think we verified that some of the other "classic" RAM-expansion carts (such as perhaps MNetwork carts) actually can use the same addresses, but I forget the details. I think the on-cart RAM in "Video Life" can use the same addresses. I can't verify any of these for myself, because I don't have the carts to load test programs on, just newer carts like the Cuttle Cart 2 and the Krokodile Cartridge. But I know for a fact that Supercat's 4A50 bankswitching uses one address space for both the reads and writes, and it should work if you're emulating one of the classic schemes on a Harmony, Krokodile, or Cuttle Cart 2.

Sdw, on Wed Nov 23, 2011 8:48 AM, said:

Another thing I've been thinking about, if I understand things correctly, 6507 only has 12-bit adressing, meaning it can adress $000-$fff.
However, how does it differentiate when adressing for example the $80-$ff area that it should go to cartridge or to built in 128-byte RAM?

The 6507 does indeed have only 12 address pins. The 2600 has lines that connect the pins of the 6507, 6532 (RIOT), and TIA chips together, so they can all "talk" to each other. The 6507 is also connected to the cartridge slot. The 6532 and the TIA actually have only a small number of addresses that they recognize, as determined by how many address pins *they* have-- for example, the TIA has only five (5) address pins! In addition to their address pins, the 6532 and TIA also have "chip select" pins, and some are connected to specific 6507 address pins, while others are connected to ground or power. These "chip select" pins are what the TIA and 6532 use to figure out if something is "talking to them." For example, if the 6507's address lines are carrying a particular address, that address is going to the TIA, 6532, and cartridge slot all at the same time, so how do the chips know when they're supposed to pay attention to the signal or ignore it? For that matter, the 6507's data pins are also connected to the TIA, 6532, and cartridge slot all at the same time. The "chip select" pins must be receiving a particular signal (high or low, depending on the pin) for the TIA or 6532 to pay attention to the incoming signals, otherwise they will just ignore the incoming signals.

Anyway, the 6502 (and hence also the 6507) expect the 1-page stack RAM to be at $0100 through $01FF, but the 2600 uses the 128 bytes of RAM on the 6532 chip as its stack RAM, which also doubles as its only built-in RAM, hence the 2600's stack is only half a page and can corrupt or be corrupted by the program RAM if the stack ever "descends" into the RAM addresses that are being used by the program. So how does the 6507 know to use addresses $0080 through $00FF for the stack, instead of $0100 through $01FF? It doesn't. The 6507 is actually trying to access $0100 through $01FF for the stack, but the way the address lines and chip select lines are all interconnected between the chips, each 16-bit memory address ends up having numerous "mirrors" or equivalent addresses. These are not separate addresses that contain identical copies of the same data-- they're actually the same memory but with different addresses, due to the fact that those addresses (through a combination of the 12-versus-16 address pins and the various chip selects) end up accessing the exact same memory location.

Edit: The 12 address pins let the 6507 address $0000 through $1FFF, not $000 through $FFF. In theory, this is 8K. But due to the way everything is wired and how the chip selects work, addresses $1000 through $1FFF always refer to the cartridge slot (hence the 4K limit on non-bankswitched carts), whereas addresses $0000 through $0FFF will refer to either the TIA or the 6532, depending on the chip select signals. But even though that appears to be 4K for the TIA and 6532, the fact that they have far fewer than 12 address pins themselves means that they can actually access only a handful of unique addresses each. So within the "full 64K address space" of the 6502, the 6507 sees these 64K as eight ( 8 ) different 8K address spaces that are actually mirrors of each other (but not "mirrors" in the sense of separate/distinct memories that all contain identical copies; all eight are the same memory). Then within the 4K portion corresponding to the TIA and 6532 addresses, the chip selects cause their handful of unique addresses to be mirrored numerous more times. So you get "mirrors within mirrors."

Edited by SeaGtGruff, Wed Nov 23, 2011 2:06 PM.

[5-11under]

The cartridge slots don't have a R/W line, so this needs to be mimicked using an address line.

[SeaGtGruff]

5-11under, on Wed Nov 23, 2011 2:05 PM, said:

The cartridge slots don't have a R/W line, so this needs to be mimicked using an address line.

Thanks for that explanation. Except using the same address to read or write a given byte of on-cart RAM does work in some cases, but not in other cases, which (as I understand it) boils down to the kind of RAM, right?

[Tjoppen]

TL;DR
The cart has no R/W line - A7 or A8 is used for that instead, hence the separate memory areas.

The 6507 has 13 adress lines (A0..12), not 12.
Page 0 has the TIA and RAM mapped to it, at $00-$2C and $80-$FF respectively
Page 1's upper half is a mirror of the lower half's RAM (A8 is ignored). Not sure if the TIA is mirrored too
Page 2 ($0200-$02FF) is used by the PIA/RIOT (upper half at least)
Pages 16-31 ($1000-$1FFF) are used for the cartridge, hence A12 == CS

What may be confusing to some is that most coders here prefer to say the ROM starts at $F000. Remember that there are no A13..15 pins though, so it's really $1000.

SeaGtGruff, on Wed Nov 23, 2011 1:51 PM, said:

... And I think we verified that some of the other "classic" RAM-expansion carts (such as perhaps MNetwork carts) actually can use the same addresses, but I forget the details. I think the on-cart RAM in "Video Life" can use the same addresses. I can't verify any of these for myself, because I don't have the carts to load test programs on, just newer carts like the Cuttle Cart 2 and the Krokodile Cartridge. But I know for a fact that Supercat's 4A50 bankswitching uses one address space for both the reads and writes, and it should work if you're emulating one of the classic schemes on a Harmony, Krokodile, or Cuttle Cart 2.

Very mysterious how that can work without an R/W pin. My guess is 4A50 uses deep knowledge of 6507 signal timings to accomplish this. The documentation I found seems to back this up: "Unlike most 2600 RAM+carts, RAM may be read and written at the same address without restriction." [1], together with only D0..7, A0..12 and power being available to the cartridge must mean something funny is going on.

[1] http://www.casperkit...lla/cartfmt.htm , "fixed" version at http://www.acc.umu.s...s/vcs/4a50.html

Edited by Tjoppen, Wed Nov 23, 2011 3:04 PM.

[Sdw]

Thanks all for the info, interesting stuff!

[SeaGtGruff]

Tjoppen, on Wed Nov 23, 2011 3:02 PM, said:

The cart has no R/W line - A7 or A8 is used for that instead, hence the separate memory areas.

When I started writing my answer, I couldn't remember the details, and kept thinking about the TIA not having any pins that are bidirectional I/O-- except for D6 and D7-- but I knew that wasn't the reason. After I posted and was reading what I'd written, I noticed Sdw's reference to $000 through $FFF and added the correction. Then I realized it had to be something related to the *cartridge* slot, but before I could add another edit I saw 5-11under's post that explained it. Thanks for the additional info!

Tjoppen, on Wed Nov 23, 2011 3:02 PM, said:

The 6507 has 13 adress lines (A0..12), not 12.

Yeah, that's another thing I missed when I was posting. I think the fact that the pins are numbered A0 through *A12* is where the confusion can arise.

Tjoppen, on Wed Nov 23, 2011 3:02 PM, said:

Page 0 has the TIA and RAM mapped to it, at $00-$2C and $80-$FF respectively
Page 1's upper half is a mirror of the lower half's RAM (A8 is ignored). Not sure if the TIA is mirrored too
Page 2 ($0200-$02FF) is used by the PIA/RIOT (upper half at least)
Pages 16-31 ($1000-$1FFF) are used for the cartridge, hence A12 == CS

Yes, the TIA is mirrored in page 1, as well as in other pages up through page 15-- not in all of them, but IIRC in half of them (0 and 1, 4 and 5, 8 and 9, etc.-- I think; I'd have to go back and look at my notes). The other half (IIRC) are mirrors for the 6532/RIOT (2 and 3, 6 and 7, etc.). Again, it's due to the way the chip selects of the TIA and 6532 are connected to the 6507 address pins. Of course, the 6532/RIOT also maps to pages 0 and 1, 4 and 5, etc., for the RAM-- but the I/O ports and timer map to pages 2 and 3, 6 and 7, etc.

Tjoppen, on Wed Nov 23, 2011 3:02 PM, said:

What may be confusing to some is that most coders here prefer to say the ROM starts at $F000. Remember that there are no A13..15 pins though, so it's really $1000.

I've gone back and forth on which I prefer to use. Since the 6502's (and hence the 6507's) interrupt vectors are at $FFFA through $FFFF-- which of course come across as $1FFA through $1FFF if you omit the upper 3 address lines (A13-A15)-- I used to prefer using $F000 as the start of the ROM area. Then I decided it was really more accurate to call it $1000. Now I'm mostly back to using $F000 again-- except it really depends on if I'm using bankswitching, since it's handy to start the different banks at $1000, or $3000, or $5000, etc., so the addresses are easier to recognize as belonging to a particular bank.

Tjoppen, on Wed Nov 23, 2011 3:02 PM, said:

SeaGtGruff, on Wed Nov 23, 2011 1:51 PM, said:

... And I think we verified that some of the other "classic" RAM-expansion carts (such as perhaps MNetwork carts) actually can use the same addresses, but I forget the details. I think the on-cart RAM in "Video Life" can use the same addresses. I can't verify any of these for myself, because I don't have the carts to load test programs on, just newer carts like the Cuttle Cart 2 and the Krokodile Cartridge. But I know for a fact that Supercat's 4A50 bankswitching uses one address space for both the reads and writes, and it should work if you're emulating one of the classic schemes on a Harmony, Krokodile, or Cuttle Cart 2.

Very mysterious how that can work without an R/W pin. My guess is 4A50 uses deep knowledge of 6507 signal timings to accomplish this. The documentation I found seems to back this up: "Unlike most 2600 RAM+carts, RAM may be read and written at the same address without restriction." [1], together with only D0..7, A0..12 and power being available to the cartridge must mean something funny is going on.

[1] http://www.casperkit...lla/cartfmt.htm , "fixed" version at http://www.acc.umu.s...s/vcs/4a50.html

Yes, the way I remember it is that it works because of the way the 6502/6507 reads/writes the data for the specified address, although I'm not technically-savvy enough about the CPU and clock cycles (phi-1 and phi-2) to have it all down pat like Supercat, batari, and others do. It does help to have a good 6502 reference-- there's one at the 6502.org site that gives a pretty good cycle-by-cycle breakdown of what happens during the instructions with different address modes.

IIRC, I had posted a simple test ROM that wrote and read to the same Superchip address to see if a single address would work for reading and writing, and the test does work in emulation, as well as when run on a Harmony cart or similar type of cart-- Krokodile or Cuttle Cart 2, etc.-- but it failed with a real Superchip. It would certainly be nice to be able to use the same addresses if possible, such as with 4A50 bankswitching, or by designing a custom scheme on a Harmony cart, etc.

[SeaGtGruff]

I was just double-checking some of my notes on the chip addresses, and the TIA *does* have mirrors on pages 2 and 3, etc. So I think the TIA has mirrors on every page from 0 to 15. And so does the 6532/RIOT, although different parts (RAM versus I/O and timer) are mirrored on different pages.

The 6532/RIOT addresses are interesting to study (IMO, anyway) because the R/W line can act as a kind of "chip select" line in some ways. For example, IIRC the address that's used to set the timer at TIM64T can also be used to *read* the timer, but it depends on whether the 6532's R/W line is high or low. So a particular address might be a write address (like TIM64T), or it might be a mirror of a read address.

This is similar to the situation with the TIA's read/write addresses, where a given address is either a write address or a mirror of one of the read addresses, since the write addresses use 5 address pins but the read addresses use only 4 address pins. So $0010 (read) is a mirror of $0000 (read), but $0010 (write) is *not* a mirror of $0000 (write).

I can see where all of this can be very confusing for some people, hence it's usually better to learn and stick to a particular set of addresses rather than get into using their mirrors-- unless the situation calls for using the mirrors, such as with 3E and 3F bankswitching. And apparently it was common for Atari programmers back in the day to use TIA read addresses that were distinct from the TIA write addresses-- $00 through $2C for writing, and $30 through $3D for reading.

[Rybags]

It seems a mystery to me that a 2600 RAM expansion could use same addresses for R/W.

I looked at one of the 6500 manuals at 6502.org and the relative timings look to be the same.

Possibly there's some way to detect what's going on ? For a read, the CPU should leave the data bus alone but a write would have definate levels on each line.

[Tjoppen]

Rybags, on Thu Nov 24, 2011 5:08 AM, said:

Possibly there's some way to detect what's going on ? For a read, the CPU should leave the data bus alone but a write would have definate levels on each line.

Ah, that makes sense. In fact, detecting that the data bus is being driven isn't terribly hard.
For each data pin you do something like put a series resistor and measure the voltage across it. If the 6507 is reading then the voltage across the resistor is zero. If there's a positive or negative voltage over the resistor then the 6507 is trying to write a bit that differs from what you're reading off of the RAM. A voltage of zero can also mean it's trying to write what is already in RAM.
If you check all eight data pins and either of them has a non-zero voltage then you've got a write. You can't detect the 6507 attempting to write what is already in that position in RAM, but that's obviously not an issue.

edit: You might have to couple the above with somewhat tricky timing logic though - probably an RC circuit to delay the write-enable (WE) signal.
Summary: Stick an XOR gate on both ends of a resistor on all data signals, OR all eight XOR outputs together and AND that with CS -> WE.

Edited by Tjoppen, Thu Nov 24, 2011 6:56 AM.

[SeaGtGruff]

SeaGtGruff, on Wed Nov 23, 2011 11:39 PM, said:

The 6532/RIOT addresses are interesting to study (IMO, anyway) because the R/W line can act as a kind of "chip select" line in some ways.

Bleah, I think "chip select" was a poor choice of words here, since it doesn't affect the selection of the chip itself. "Address select" is more accurate-- or "in-chip select," selecting between different registers that have the same address within the chip.

[SeaGtGruff]

Rybags, on Thu Nov 24, 2011 5:08 AM, said:

It seems a mystery to me that a 2600 RAM expansion could use same addresses for R/W.

You might be able to find out more by searching the forums for "magic writes" in posts by Supercat, since IIRC that was the term he used to describe it.

[SeaGtGruff]

Crud, last night I realized I was confusing two different issues-- (1) using the same addresses for read/write and (2) executing code in RAM. The tests I was referring to were for executing code in RAM, *not* for reading and writing RAM at the same addresses! So forget what I said about that, with the exception that it *does* work with the 4A50 bankswitching thanks to "magic writes." On the other issue, executing code in RAM doesn't work with a real Superchip, but does work on carts like the Harmony that are imitating one of the Superchip bankswitching schemes. It's also used in "Video Life."