OK, for each scanline there are 228 TIA clock cycles or 76 CPU cycles.
According to this Website: lda zero page,x is four clock cycles and sta zero page is three clock cycles, so a pair is seven clock cycles.
For the basic routine to display a 40x192 image I have 6 pairs (three read/write for the left side of the playfield, and three read/write for the right side of the playfield. That makes 7 * 6 = 42 cycles.
I also have two SLEEP 4 statements so that's an extra 8 cycles so 50 cycles altogether.
The last part of the code is
sta WSYNC
inx
cpx #192
bne VisibleScreen
Now it seems to me that the since the last three opcodes are after WSYNC then they're inbetween scanlines and shouldn't count towards the 76 cycles, right?
If so then the sta WSYNC should be 3 cycles, so that's a total of 53 cycles and I should have 76 - 53 = 23 cycles left.
If those opcodes do count, then that's an extra 6 or 7 cycles, so at most 53 + 7 = 60 and 76 - 60 = 16 cycles left.
Yet, inbetween the last sta PF2 and sta WSYNC if use anything more than 11 cycles the screen goes wonky. So I am I incorrect about the timing, doing bad math, or...?
Thank you.














