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Session 17: Asymmetrical Playfields - Part 1


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#51 xucaen OFFLINE  

xucaen

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Posted Tue Jan 18, 2005 10:15 PM

Thank you Andrew and Thomas, I do understand now. and to figure out where I went wrong I picked up the stella guide again for the 20+Nth time and I read the following..

Quote

Simply writing to the WSYNC causes the microprocessor to halt until the electron beam reaches the right edge of the screen, then the microprocessor resumes operation at the beginning of the 68 color clocks for horizontal blanking.  

For some reason I had thought it meant wsync halts the cpu until the beam reaches the left side of the screen. So you see why I was confused... it's good to know that I do have those 68 clocks (68/3=22.667 cycles) to use for game logic after all. Very cool. 8)

Jim

#52 supercat OFFLINE  

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Posted Thu Jun 2, 2005 10:50 PM

Andrew Davie, on Wed Jun 25, 2003 7:51 AM, said:

Our 'zero point' of any scanline is the beginning of horizontal retrace.  This is the point at which the TIA re-enables the 6502 if it has been halted by a WSYNC write.  At the beginning of any scanline, then, we know that we have exactly 68 colour clocks (=68/3 = 22.667 cycles) before the TIA starts 'drawing' the line itself.

Is that the start of horizontal RETRACE or horizontal BLANKING? My recollection is that the TIA reenables the 6507 when the electron beam hits the right-side border, which is actually a fair bit before the beam actually starts sweeping left. I fully appreciate that it's often useful to regard a scan line as starting as soon as the displayed portion of the previous one ends (indeed, that's how I've drawn timing charts when working out code) but in some goofy cases the distinction might be important.

BTW, would STA $xx be suitable for use as a three-cycle NOP, where $xx is a non-existent TIA write register? I know that some registers like $3F may be used for some bank-switching carts, but I would think some should be available.

#53 Cybergoth OFFLINE  

Cybergoth

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Posted Fri Jun 3, 2005 1:09 AM

Hi there!

supercat, on Fri Jun 3, 2005 4:50 AM, said:

BTW, would STA $xx be suitable for use as a three-cycle NOP, where $xx is a non-existent TIA write register?  I know that some registers like $3F may be used for some bank-switching carts, but I would think some should be available.

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For a three cycle delay you can just use
SLEEP 3

Greetings,
Manuel




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