5 replies to this topic

[robware]

I've been playing around a little with sprite positioning, and I'm confused by the results I get from the following code.

STA WSYNC
SLEEP 20 ; 20
STA RESP0 ; 3

My thinking is that the WSYNC register is hit on the final cycle of the STA
instruction, so when the processor resumes, the TIA should be on colour clock #0. Now 20 cycles are burned, and then the RESP0 register is
hit on the final cycle of the STA instruction. This means that PL0 is reset
at CPU cycle 23, or TIA cycle 69.

So i'm expecting the player to start drawing 1 pixel from the left of the display, since there are 68 TIA cycles in the horizontal blank. However, on Z26 and Stella the PL0 sprite seems to draw 8 or 9 pixels from the left edge. Can anyone help me understand why this is happening ?

I'll post the binary and source if to the code if it helps, just I'm at work at the moment.

Many thanks,
Rob

[EricBall]

The STA RESPn doesn't take effect for several cycles after when you expect it. Trust Z26.log, it's correct.

[robware]

Thanks for your reply Eric.

Is there any documentation on the exact length and nature of this delay? Is the delay just in the graphics appearing, or in the GRP0 register being read by the TIA? In other words, should a change made to GRP0 immediately AFTER a latched reset cause the displayed graphics to be altered due to this delay? Sorry to be so nitpicking, but its for a good reason

[DEBRO]

robware said:

Is there any documentation on the exact length and nature of this delay?

You may want to take a look at Andrew Towers' TIA Hardware Notes. This should give you what you're looking for.

[robware]

thanks! i've never seen that document before, looks like just the thing

[DEBRO]

robware said:

thanks! i've never seen that document before, looks like just the thing  

Ahhh...looks like you should join [stella] if you're not already a member