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Bob
boisy, on Fri Feb 3, 2012 10:04 AM, said:
Ok, things have gotten a little more complicated than I thought.
It appears that the RC time constant approach to generating E from Q is not working as noted in the video above. In fact, in talking with a friend who knows hardware well, he thinks the resistor/capacitor time constant approach is flawed and will only yield problems in a mass produced product environment.
His recommendation would be to tie in directly to the 14MHz clock on the Atari, and use a CPLD to detect the leading edge of PHI0, then count the number of 14MHz crystal oscillations until we get a quarter way into the PHI0 cycle. The CPLD would then assert an output pin high (the E clock) for a predetermined time, then drop it, and wait for the next rise of PHI0.
I don't like this approach because it adds complexity of a CPLD, and also would require a physical wiring between the crystal and the satellite board. That's not something I would want to do. I want to be able to generate the required clocking right from PHI0 coming in from pin 37 of the CPU socket, and do it consistently.
He also mentioned the possibility of using a PLL, but he wasn't an expert on phase locked loops.
Anyone here have some input on the best approach to use at this point?
It appears that the RC time constant approach to generating E from Q is not working as noted in the video above. In fact, in talking with a friend who knows hardware well, he thinks the resistor/capacitor time constant approach is flawed and will only yield problems in a mass produced product environment.
His recommendation would be to tie in directly to the 14MHz clock on the Atari, and use a CPLD to detect the leading edge of PHI0, then count the number of 14MHz crystal oscillations until we get a quarter way into the PHI0 cycle. The CPLD would then assert an output pin high (the E clock) for a predetermined time, then drop it, and wait for the next rise of PHI0.
I don't like this approach because it adds complexity of a CPLD, and also would require a physical wiring between the crystal and the satellite board. That's not something I would want to do. I want to be able to generate the required clocking right from PHI0 coming in from pin 37 of the CPU socket, and do it consistently.
He also mentioned the possibility of using a PLL, but he wasn't an expert on phase locked loops.
Anyone here have some input on the best approach to use at this point?
