supercat

SeaGtGruff, on Sat Jul 23, 2011 4:51 PM, said:

The counters reset when they reach the programmed count value. The left set of boxes is the AUDFx register, each bit of which is equipped with inverted and non-inverted outputs. Each stage of the counter is likewise equipped with inverted and non-inverted outputs. The leftmost vertical line through the larger, right-side, set of boxes, will be pulled to ground if any counter bit disagrees with its corresponding AUDFx bit. That signal is delayed by two pass gates and then fed vertically, between the two clock wires, as one of the three-inputs to a NOR gate to clear all the counter stages.

Incidentally, in the places where you see a grid of wires with circles at some of the intersection, each circle is a transistor. The gate will generally be the horizontal wire and the drain will be the vertical wire. The source will be connected to ground (as with other gates, the ground connection is not explicitly drawn). The simplest way to think about such grids is that a column will be pulled down if row where it has a circle is high. This style of logic requires the same amount of space whether all the intersections have circles or none of them do. On the other hand, such grids can be laid out very compactly. Something like the collision-detect logic uses a 30 transistors in a 5x15 grid to detect collisions. Even though 75 transistors could fit in the space that's used for 30, trying to individually wire the 30 transistors would likely use more space than putting them in the grid.

SeaGtGruff, on Wed Jul 20, 2011 8:29 PM, said:

To understand transistor sizes, first understand that current in amps is the number of coulombs of electrons per second; capacitance in farads is the number of coulombs of electrons that will be required to produce a volt of back pressure. Transistor gates have a certain amount of capacitance, and they must reach a certain voltage to switch; that means they must have a certain number of electrons flow into or out of the gate. If the current flowing into or out of the gate is low, it may take awhile for enough electrons to flow to switch the transistor.

Bigger transistors will allow more current to flow when they're turned on, but they will also have higher gate capacitance than smaller transistors.

Here's what I think is going on with the schematic at the top of the page. The clock signal will have to drive a lot of stuff on the chip, so it uses the indicated circuit to drive it strongly high and low. Note that the big bold resistor is probably as low a value as the engineers could practically produce, but the diffusion material has a non-trivial amount of resistance no matter what one does.

A normal NMOS inverter contains a single transistor which pulls the output low whenever the input is high, and a passive pullup resistor which tries to pull the output high always, and succeeds when the transistor doesn't overpower it. NMOS design using such simple gates involves a tradeoff between using a low-value resistor, which will waste a lot of power, dissipate a lot of heat, and require a pull-down transistor strong enough to overpower it, or else using a high-value resistor which can't pull the output very fast. I believe that the side wire on a gate isn't a normal 3-state control, but rather operates a transistor in series with the high-side resistor (which can then be much smaller). Note that if the 'side' wire and the input were both high simultaneously, the gate would draw substantial additional current, since the pull-up transistor's efforts to pull the line high would be much stronger than those of a passive pull-up resistor. One should note that while pull-up transistors can switch more current than pull-up resistors when their outputs are far below their gates, NMOS pull-up transistors get very wimpy when the output voltage approaches the gate voltage. Still, since most NMOS gates will switch at voltages more than two volts below VDD, it's possible to construct a reasonably powerful signal driver by using a small gate to drive a pull-up transistor output for a much larger gate. For signals like Clk which are distributed throughout much of the chip, this is important.

The TIA is implemented with NMOS technology, meaning everything is built from one style of transistor: a Negative-channel Metal Oxide Semiconductor Field Effect Transistor (also called an N-channel MOSFET or NFET). An NFET has three terminals: the source and drain, which are in this context interchangeable (typically the side closer to VDD will be labeled the source, and the other end the drain; power NFETs are generally constructed asymmetrically, and the distinction is important, but within a chip like the TIA it doesn't matter), and the gate. An NFET will connect the source and drain ends whenever the gate is 1-2 volts more positive than the less-positive end, and behave as an insulator otherwise. Note that while the voltage on the gate connects or disconnects the source and drain from each other, almost no current flows into or out of the gate itself. Note also that if one end (e.g. the source) of the MOSFET is ground and the gate is high, the MOSFET will strongly connect the other end to ground, but if the drain is tied to VDD and the gate is also at VDD, it will only pull the source weakly (as the source is pulled toward VDD, the voltage difference between the gate and source will drop so the transistor will start conducting less well).

An NMOS inverter consists of an NFET to ground and a resistor to VDD. A NAND gate consists of two NFETS in series connected to ground, along with a resistor to VDD. A NOR gate consists of two NFETs in parallel connected to ground, along with a resistor to VDD.

The D1 block consists of two inverters (each of which is a transistor to ground and a resistor to VDD), along with two discrete transistors. When the gate of a discrete transistor is high, it will act as a closed switch (though it is more effective at passing logic '0's than logic '1's). When the gate is low, it will act as an open switch. Because very little current flows into or out of a MOSFET gate, opening the switch connected to the MOSFET gate will cause the gate to simply remain in whatever state it's in, at least for awhile. Effectively, the transistor and inverter form a crude latch. Such a latching circuit is much smaller and simpler than a more 'conventional' latch using a couple of NOR gates (four transistors) but it has the disadvantage of only holding information for a few dozen microseconds. If you look in the TIA design, though, you'll notice that in all the places such latching circuits are used they'll be strobed pretty frequently, typically using a non-overlapping two-phase clock.