ANTIC on a Breadboard

[UNIXcoffee928]

This thread is for describing methods of accurately reverse-engineering the ANTIC, so that it may first be described & documented on a breadboard, and then, may be used to facilitate a model that can be used in a FPGA description language.

 

This idea came to life in the "Atari on a Breadboard" thread, but will be treated as a separate concept, to keep the threads from becoming distracting & cluttered.

 

Here are the links to all related threads in this "Brute Force Initiative":

 

- Atari on a Breadboard

- POKEY on a Breadboard

- ANTIC on a Breadboard

- SALLY on a Breadboard

- GTIA on a Breadboard

- PIA on a Breadboard

 

- Full Atari Documentation for the ANTIC in .pdf format

 

 

=========================================================
ANTIC
=========================================================
           _________
          |   | |   |
          |    -    |
01. Vss   -| 01   40 |- 40. D4
02. AN0   -| 02   39 |- 39. D5
03. AN1   -| 03   38 |- 38. D6
04. LP    -| 04   37 |- 37. D7
05. AN2   -| 05   36 |- 36. RST
06. RNMI  -| 06   35 |- 35. FØ0
07. NMI   -| 07   34 |- 34. Ø0
08. REF   -| 08   33 |- 33. D3
09. HALT  -| 09   32 |- 32. D2
10. A3    -| 10   31 |- 31. D1
11. A2    -| 11   30 |- 30. D0
12. A1    -| 12   29 |- 29. Ø2
13. A0    -| 13   28 |- 28. A4
14. R/W   -| 14   27 |- 27. A5
15. RDY   -| 15   26 |- 26. A6
16. A10   -| 16   25 |- 25. A7
17. A12   -| 17   24 |- 24. A8
18. A13   -| 18   23 |- 23. A9
19. A14   -| 19   22 |- 22. A11
20. A15   -| 20   21 |- 21. Vcc
21. Vcc    |_________|
          |  ANTIC  |
          |_________|

 

=========================================================
ANTIC  (Pins run 0-20 on left & 40-21 on the right)
=========================================================
01. Vss:    Ground
02. AN0:    CTIA/GTIA bus    0 (data type unknown)
03. AN1:    CTIA/GTIA bus    1 (data type unknown)
04. LP:     Light pen input
05. AN2:    CTIA/GTIA bus    2 (data type unknown)
06. RNMI:   Non-maskable interrupt input
07. NMI:    Non-maskable interrupt output (to CPU)
08. REF:    RAM refresh output
09. HALT:   Halt output; suspends the CPU while ANTIC reads memory
10. A3:     Memory addr bus  3
11. A2:     Memory addr bus  2
12. A1:     Memory addr bus  1
13. A0:     Memory addr bus  0
14. R/W:    Read/write direction
15. RDY:    ANTIC pulls this pin low to halt the CPU when the WSYNC register is written, until the next horizontal blank occurs.
16. A10:    Memory addr bus 10
17. A12:    Memory addr bus 12
18. A13:    Memory addr bus 13
19. A14:    Memory addr bus 14
20. A15:    Memory addr bus 15
21. Vcc:    +5V power
22. A11:    Memory addr bus 11
23. A9:     Memory addr bus  9
24. A8:     Memory addr bus  8
25. A7:     Memory addr bus  7
26. A6:     Memory addr bus  6
27. A5:     Memory addr bus  5
28. A4:     Memory addr bus  4
29. Ø2:     Phase 2 input clock
30. D0:     Memory data bus  0
31. D1:     Memory data bus  1
32. D2:     Memory data bus  2
33. D3:     Memory data bus  3
34. Ø0:     Phase zero clock output
35. FØ0:    Fast phase 0 input clock
36. RST:    Resets ANTIC
37. D7:     Memory data bus  7
38. D6:     Memory data bus  6
39. D5:     Memory data bus  5
40. D4:     Memory data bus  4

 

 

Welcome Aboard!

Edited November 11, 2008 by UNIXcoffee928

[PacMan]

I'm not exactly sure why you would want to breadboard it. When I was doing some research on the Atari 8-bit architecture I simply took apart an 800XL and put some DIP extenders on the chips and hooked a logic analyzer to them. This way I could load any software I needed and also simply develop and try out program that set all the chips to their respective desired mode of operation.

 

It was great fun though and extremely rewarding.

[Rybags]

Of all the custom ICs (Antic, CTIA, Pokey), I actually reckon Antic would probably be the easiest to work out.

 

The AN0-AN2 bus is reasonably well documented - the only mysteries would be the timing of stuff like begin graphics and H/VSync, although they are documented in the Hardware Manual.

 

The Display List is pretty simple in operation, Player-Missile data fetches are also simple. GTIA by far does a lot of the grunt work so far as generating the display itself.

 

Horizontal scrolling is another somewhat tricky area - there is DMA delay involved as well as variable number of DMA fetches depending on what scroll value is in effect.

 

Another thing possibly not well understood or documented is the effect of changing HScrol register on the fly (middle of a scanline).

 

The Antic DMA Timings.txt document uploaded elsewhere around here would be of help if you want to reverse-engineer Antic.

[atariksi]

Of all the custom ICs (Antic, CTIA, Pokey), I actually reckon Antic would probably be the easiest to work out.

 

The AN0-AN2 bus is reasonably well documented - the only mysteries would be the timing of stuff like begin graphics and H/VSync, although they are documented in the Hardware Manual.

 

The Display List is pretty simple in operation, Player-Missile data fetches are also simple. GTIA by far does a lot of the grunt work so far as generating the display itself.

 

Horizontal scrolling is another somewhat tricky area - there is DMA delay involved as well as variable number of DMA fetches depending on what scroll value is in effect.

 

Another thing possibly not well understood or documented is the effect of changing HScrol register on the fly (middle of a scanline).

 

The Antic DMA Timings.txt document uploaded elsewhere around here would be of help if you want to reverse-engineer Antic.

 

Where's the Atari Hardware Manual being sold or available? All the ANTIC stuff I programmed, I had to go by Mapping the Atari or experimentation. For example, start off by doing LDA/STA ColorReg with all ANTIC DMAs disabled gives you 105 cycles of the 114 available per scan line (9 being lost to memory refresh somewhere). The bigger bands of color occur where the memory refresh cycle occurs and then you shift by one cycle and see the color bands again. Thus, you can narrow down to where the memory refresh cycle occurs. Gradually, you enable a DMA (like missile, instruction fetch, sprites, ...) and see the effect of cycle reduction and color band increase.

[Rybags]

http://www.atariage.com/forums/index.php?showtopic=127483

 

I started that thread - it's got a whole bunch of manuals including the OS and Hardware Manuals.

[Rybags]

OK... going by "Antic Timings" and the Vertical/Horizontal architecture diagram from the Hardware Manual."

 

"A frame in the life of Antic" WIP...

 

Set VSync, Reset VSync, Reset VCTR. Send VSync command on AN0-AN2 to GTIA. Reset internal line counter.

 

Do X number of black lines. PAL has 72 non-display lines, NTSC has 22 (split evenly between top/bottom of screen? )

 

Display Area 240 scanlines where software has control over the screen display.

 

Cycle 0 - (DMA) Read Display List Instruction if DList DMA enabled AND an instruction not in progress.

This cycle may also be used to fetch Missile Data in some cases.

Cycle 1-4 (DMA) If Player DMA is enabled, then fetch Player Data. Player Data is fetched every line regardless if 1 or 2-line resolution.

2 line resolution merely repeats each read twice in succession.

Cycle 5-6 (DMA) If Display List instruction has been read and it is a 3-byte instruction, read the address portion now.

Cycles 7-9 Never used for DMA

Cycle 10 (DMA) First character fetch cycle if Widescreen DMA is enabled, without VSCROL or VSCROL = 0

In 40 column character mode, 2 characters are prefetched before the first graphics fetch.

Cycle 105 is the last possible screen DMA fetch position.

Refresh cycles not predetermined, can vary in number and position dependant on screen width, and if "badline" in 40-column text modes.

 

Screen display (horizontal)

Dependant on width in DMACTL, and whether HScrolling enabled.

Certain phenonema occur on l/r of screen if widescreen and HScroll enabled.

Changing DMA mode mid-line seems to have immediate effect.

Changing HScrol mid-line has "unknown" artifacting results.

 

Cycle 112 used for missile DMA... cycle 0 used in preference to this cycle if DList instruction fetch is not needed ?

 

Graphics mode display logic

Antic uses DCTR (Delta counter)... counts from 0 to n (n dependant on mode, and can vary when VScrol in progress).

When DCTR hits target value, Antic then knows that a DList Instruction fetch becomes due at the commencement of the next scanline.

If DList Instruction DMA is not enabled, Antic will reuse the previous value.

Untested if only graphics mode is carried over, or also V/H Scrolling state, or Interrupt request bit.

 

...

Edited November 6, 2008 by Rybags

[peteym5]

I'm not exactly sure why you would want to breadboard it....

 

It was great fun though and extremely rewarding.

 

 

I am not sure what the point would be also. Honestly I would have like to have seen Atari put forth their ideal of combining the ANTIC and GTIA in one chip, (CGIA). There has not been a whole lot of documentation on it or why Atari did not decide to go with it. It would have reduced the 5200, XLs and XEs down in price even further. I remember reading somewhere that it took less cycles from the main BUS and they might have fixed the issue with having 16 instead of 8 lumas available for the non-GTIA modes. A few things were probably done in that chip we don't know about. They probably were considering making a better video chip that was backward compatible. Another possibility is having all the registers mapped on a single page but would end up loosing more backward compatibility with the 400/800

[atariksi]

OK... going by "Antic Timings" and the Vertical/Horizontal architecture diagram from the Hardware Manual."

 

"A frame in the life of Antic" WIP...

 

Set VSync, Reset VSync, Reset VCTR. Send VSync command on AN0-AN2 to GTIA. Reset internal line counter.

 

Do X number of black lines. PAL has 72 non-display lines, NTSC has 22 (split evenly between top/bottom of screen? )

 

Display Area 240 scanlines where software has control over the screen display.

 

Cycle 0 - (DMA) Read Display List Instruction if DList DMA enabled AND an instruction not in progress.

This cycle may also be used to fetch Missile Data in some cases.

Cycle 1-4 (DMA) If Player DMA is enabled, then fetch Player Data. Player Data is fetched every line regardless if 1 or 2-line resolution.

2 line resolution merely repeats each read twice in succession.

...

 

The VDELAY would require the same data to be read repeatedly in 2 line resolution since entire thing could get shifted by one scan line at any time even at mid-scanline.

Where are you defining your cycle 0 on the scan line? Or what cycle # do you attribute to the first pixel say in standard GITA 80*200 mode?

[DanBoris]

I am not sure what the point would be also. Honestly I would have like to have seen Atari put forth their ideal of combining the ANTIC and GTIA in one chip, (CGIA). There has not been a whole lot of documentation on it or why Atari did not decide to go with it.

 

Actually the technical document on it is available, you can find it here:

 

http://www.retromicro.com/files/atari/8bit/cgia.pdf

 

It was not much more then an ANTIC and GTIA on the same piece of silicon. It moved a few other support components on to the chip, but was software compatible, including addressing, to the separate ANTIC and GTIA.

 

Dan

[Rybags]

The cycle names I was mentioning came from the document...

 

Antic_Timings.txt

 

So, cycles correspond to colour clocks / 2. Colour clocks correspond exactly to HPOS for Player/Missiles.

 

VDelay is performed by GTIA, not Antic.

 

1 and 2 line PMG resolution should be a simple affair. All it means is the offsets from PMBASE is different and 2-line bumps the address counter every second line rather than every line.

 

On the GTIA side, a bit set in VDelay simply means that GTIA doesn't reload the GRAF register for that object during even numbered scanlines - Antic still does DMA every scanline for PMGs regardless of which resolution is selected.

 

VDelay not set should mean that an object is still reloaded during odd scanlines - that would have to be tested by altering PMG images in RAM to verify.